Preserving read look ahead data in auxiliary latches

Patent metadata

Field	Value
Publication number	US-10025532-B2
Application number	US-201514928188-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Sep 11, 2015
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

First claim

We claim:

1. A method for pre-fetching data, the method comprising:
performing the following in a storage system comprising a controller and a memory die comprising a non-volatile memory, a spare latch, and a transfer data latch (XDL), wherein the non-volatile memory, spare latch, and XDL are in the memory die and not in the controller:
predicting an address to be read from the non-volatile memory;
pre-fetching data from the predicted address in the non-volatile memory and storing the data

in the spare latch in the memory die;
receiving a plurality of read commands, each read command comprising an address;
determining that an address in one of the plurality of read commands matches the predicted address; and
prioritizing the one of the plurality of read commands over other read commands in the plurality of read commands by:
moving the data from the spare latch in the memory die to the XDL in the memory die; and
transferring the data from the XDL in the memory die to the controller.

2. The method of claim 1 transferring the data from the controller to a host.

3. The method of claim 1 , wherein the spare latch is configured to temporarily hold the data before the data is moved to the XDL.

4. The method of claim 1 , wherein only the XDL can transfer the data out of the memory device.

5. The method of claim 1 , wherein the predicted address is predicted from a prior read address.

6. The method of claim 1 wherein the predicting is based on a sequence of data previously requested by a host.

7. The method of claim 1 wherein the non-volatile memory array comprises a three-dimensional memory.

8. A memory die comprising:
a non-volatile memory array;
a transfer data latch (“XDL”);
one or more spare latches; and
pre-fetch circuitry configured to pre-fetch data for a future read request from the non-volatile memory array, store the pre-fetched data in the one or more spare latches, receive a plurality of read commands, each read command comprising an address, determine that an address in one of the plurality of read commands matches the predicted address, and prioritizing the one of the plurality of read commands over other read commands in the plurality of read commands by: moving the data from the spare latch in the memory die to the XDL in the memory die; and transferring the data from the XDL in the memory die out of the memory.

9. The memory die of claim 8 further comprising prediction circuitry configured to predict the future read request.

10. The memory die of claim 8 , wherein the non-volatile memory array comprises a three-dimensional memory.

11. The memory die of claim 8 wherein the pre-fetch circuitry is configured to store the pre-fetched data in two or more of the spare latches in parallel.

12. A memory system comprising:
a controller; and
a memory die in communication with the controller, wherein the memory die comprises:
a non-volatile memory array;
a data transfer latch (XDL);
one or more auxiliary latches; and
circuitry configured to:
cache, in the one or more auxiliary latches, data from the non-volatile memory array that is predicted to be requested by the controller in the future;
receive a plurality of read commands, each read command comprising an address;
determine that an address in one of the plurality of read commands matches the predicted address; and
prioritize the one of the plurality of read commands over other read commands in the plurality of read commands by:
moving the data from the spare latch in the memory die to the XDL in the memory die; and
transferring the data from the XDL in the memory die y to the controller.

13. The memory system of claim 12 , wherein the data is cached by storing the data in two or more of the auxiliary latches in parallel.

14. The memory system of claim 12 , wherein only the XDL is configured to transfer data to the controller.

15. The memory system of claim 12 , wherein the one or more auxiliary latches comprise a read look ahead cache.

16. The memory system of claim 12 , wherein the data predicted to be requested comprises data identified from a data sequence in prior read requests.

17. The memory system of claim 12 further comprising at least one additional memory die, wherein each additional memory die has its own data transfer latch (XDL) and its own one or more auxiliary latches.

18. A memory system comprising:
a memory die comprising a non-volatile memory, a spare latch, and a transfer data latch (XDL);
means for predicting an address to be read from the non-volatile memory;
means for pre-fetching data from the predicted address in the non-volatile memory and storing the data in the spare latch;
means for receiving a plurality of read commands, each read command comprising an address;
means for determining that an address in one of the plurality of read commands matches the predicted address; and
means for prioritizing the one of the plurality of read commands over other read commands in the plurality of read commands by:
moving the data from the spare latch in the memory die to the XDL in the memory die; and
transferring the data from the XDL in the memory die to the controller.

19. The memory system of claim 18 further comprising at least one additional memory die, wherein each additional memory die has its own data transfer latch (XDL) and spare latch.

20. The memory system of claim 18 , wherein the non-volatile memory array comprises a three-dimensional memory.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Manohar Abhijeet
• Tuers Daniel E
• Deshe Noga
• Kelner Vered
• Vishne Gadi
• Appel Nurit
• Hahn Judah Gamliel

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title