Data transfer between asynchronous clock domains

Patent metadata

Field	Value
Publication number	US-10025343-B2
Application number	US-201113991602-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

First claim

What is claimed is:

1. A processor, comprising:
first and second clock domains to be clocked by first and second asynchronous clock signals, respectively;
first logic to transfer data between the first and second clock domains in response to a synchronization signal, each cycle of the synchronization signal corresponding to a fixed multiple of first clock signal cycles, wherein the synchronization signal is to be propagated from the first clock domain to the second clock domain to transfer a buffer write pointer from the first clock domain to the second clock domain, and then from the second clock domain to the first clock domain to transfer a buffer read pointer from the second clock domain to the first clock domain; and
second logic to indicate cycles of the second clock signal that correspond to the synchronization signal.

2. The processor of claim 1 , wherein the synchronization signal comprises a single bit.

3. The processor of claim 1 , wherein the synchronization signal comprises a repeating pulse.

4. The processor of claim 1 , wherein:
the synchronization signal comprises multiple bits; and
the first logic comprises transfer registers corresponding to the multiple bits of the synchronization signal.

5. The processor of claim 1 , further comprising an elastic buffer to be accessed asynchronously by the first and second clock domains, wherein the data exchanged between the first and second clock domains comprises one or more pointers to the elastic buffer.

6. The processor of claim 1 , further comprising an elastic buffer to be accessed asynchronously by the first and second clock domains, wherein the data exchanged between the first and second clock domains comprises read and write pointers associated with the elastic buffer.

7. The processor of claim 1 , wherein the synchronization signal is to be propagated from the first clock domain to the second clock domain, and then from the second clock domain to the first clock domain.

8. The processor of claim 1 , wherein the synchronization signal is synchronous with the first clock signal.

9. The processor of claim 1 , further comprising a frequency divider to generate the synchronization signal in response to the first clock signal.

10. A system, comprising:
a buffer to transfer data between first and second clock domains, wherein the first and second clock domains are clocked by first and second cyclical clock signals, respectively, and wherein the buffer is indexed by one or more buffer pointers;
a synchronization clock to generate a synchronization signal based at least in part on the first clock signal, each cycle of the synchronization signal corresponding to a fixed multiple of first clock signal cycles;
synchronization logic to transfer the one or more buffer pointers between the first and second timing domains in response to the synchronization signal, wherein the synchronization signal is to be propagated from the first clock domain to the second clock domain to transfer a buffer write pointer from the first clock domain to the second clock domain, and then from the second clock domain to the first clock domain to transfer a buffer read pointer from the second clock domain to the first clock domain; and
reporting logic to indicate correlation of the second clock signal to the synchronization signal.

11. The system of claim 10 , wherein the synchronization signal comprises a single bit.

12. The system of claim 10 , wherein the synchronization logic comprises multiple transfer registers.

13. The system of claim 10 , wherein the synchronization signal comprises pulses, and wherein the reporting logic is to indicate how many cycles of the second clock signal correspond to each of the pulses.

14. The system of claim 10 , wherein the buffer comprises a first-in-first-out buffer, and the buffer pointers comprise read and write pointers.

15. The system of claim 10 , wherein the synchronization clock comprises a frequency divider to generate the synchronization signal in response to at least the first clock signal.

16. The system of claim 10 , wherein the synchronization signal is to be propagated from the first clock domain to the second clock domain, and then from the second clock domain to the first clock domain.

17. The system of claim 10 , wherein the synchronization signal is to be synchronous with the first clock signal.

18. A method, comprising:
clocking a first clock domain with a first cyclical clock signal;
clocking a second clock domain with a second cyclical clock signal, wherein the first and second cyclical clock signals are asynchronous;
generating a synchronization signal based at least in part on the first clock signal, each cycle of the synchronization signal corresponding to a fixed multiple of first clock signal cycles;
propagating the synchronization signal from the first clock domain to the second clock domain and back to the first clock domain;
transferring data between the first and second clock domains in response to the synchronization signal; and
reporting correspondence between the synchronization signal and cycles of the second clock signal.

19. The method of claim 18 , further comprising generating the synchronization signal in synchronization with the first clock signal.

20. The method of claim 18 , wherein the synchronization signal comprises cycles that are synchronous with the first clock signal, and the reporting comprises indicating how many cycles of the second clock signal occur during each cycle of the synchronization signal.

21. The method of claim 18 , further comprising:
transferring a first buffer pointer from the first clock domain to the second clock domain in response to propagating the synchronization signal from the first clock domain to the second clock domain; and
transferring a second buffer pointer from the second clock domain to the first clock domain in response to propagating the synchronization signal back to the first clock domain.

Assignees

• Rifani Michael C
• Kyker Alan B
• Geist Alan S
• Lee David M
• Intel Corp

Inventors

• Rifani Michael C
• Kyker Alan B
• Geist Alan S
• Lee David M

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title