Charge pump voltage regulator
US-2017288532-A1 · Oct 5, 2017 · US
US10024887B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10024887-B2 |
| Application number | US-201615245882-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 24, 2016 |
| Priority date | Aug 24, 2016 |
| Publication date | Jul 17, 2018 |
| Grant date | Jul 17, 2018 |
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Circuitry and methods for measuring the voltage at a node are disclosed. A capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.
Opening claim text (preview).
What is claimed is: 1. Circuitry for analyzing the voltage at a node, the circuitry comprising: a capacitor divider coupled to the node, the capacitor divider having a first output, wherein voltages at the first output are proportional to first voltages at the node; a resistive divider coupled to the node, the resistive divider having a second output, wherein voltages at the second output are proportional to second voltages at the node, the second voltages being different from the first voltages; first switching circuitry coupled to the capacitor divider for: activating the capacitive divider when the first voltages are at the node; and disabling the capacitor divider when the first voltages are not at the node; and second switching circuitry coupled to the resistive divider for: activating the resistive divider when the second voltages are at the node; and disabling the resistive divider when the second voltages are not at the node. 2. The circuitry of claim 1 , wherein the capacitor divider includes a first capacitor coupled between the node and the first output and at least one second capacitor coupled to the first output. 3. The circuitry of claim 1 , wherein the capacitor divider includes a first capacitor coupled between the node and the first output and a plurality of second capacitors coupled to the first output by switches for selectively coupling individual capacitors in the plurality of second capacitors to the first output. 4. The circuitry of claim 3 , wherein the plurality of second capacitors are selectively coupled to the first output to obtain a predetermined voltage at the first output. 5. The circuitry of claim 4 , further comprising circuitry for determining the voltage at the node in response to the capacitance selectively coupled to the first output. 6. The circuitry of claim 5 , further comprising a comparator for comparing the voltage at the first output to a predetermined voltage, the output of the comparator being coupled to the circuitry for determining the voltage at the first output. 7. The circuitry of claim 1 , further comprising a sample and hold circuit coupled to the second output. 8. The circuitry of claim 1 further comprising a clamp control coupled to the first switching circuitry and the second switching circuitry for controlling the states of the first switching circuitry and the second switching circuitry in response to an input signal. 9. The circuitry of claim 8 , wherein the input signal is a pulse width modulated signal. 10. The circuitry of claim 1 , wherein the node is coupled to one of a source or drain of a transistor. 11. The circuitry of claim 10 , wherein the gate of the transistor is driven at least partially in response to the voltage at the first output and the voltage at the second output. 12. A method for determining the voltage at a node, the method comprising: coupling a capacitive divider to the node during a period when a first voltage is at the node and decoupling the capacitive divider from the node when the first voltage is not at the node; outputting a first signal proportional to the first voltage at the node from the capacitive divider on a first output; coupling a resistive divider to the node during a period when a second voltage is at the node, wherein the first voltage is greater than the second voltage, and decoupling the resistive divider from the node when the second voltage is not at the node; outputting a second signal proportional to the second voltage at the node from the resistive divider on a second output. 13. The method of claim 12 wherein outputting signals proportional to the first and second voltages at the node includes outputting signals from successive first voltages and second voltages on the node. 14. The method of claim 12 , wherein outputting a first signal proportional to the first voltage at the node from the capacitive divider on a first output comprises: coupling a first capacitor between the node and the first output; coupling at least one second capacitor to the first output; measuring the voltage at the first output; changing the capacitance of the at least one second capacitor until the voltage at the first output is a predetermined voltage; and determining the voltage at the node in response to the value of the first capacitor and the value of the at least one second capacitor. 15. The method of claim 12 , wherein outputting a first signal proportional to the first voltage at the node from the capacitive divider on a first output comprises: coupling a first capacitor between the node and the first output; coupling at least one second capacitor to the first output; measuring the voltage at the first output; changing the capacitance of the at least one second capacitor continually during subsequent periods when the first voltage is present at the node until the voltage at the first output is a predetermined voltage; and determining the voltage at the node in response to the value of the first capacitor and the value of the at least one second capacitor. 16. The method of claim 12 , wherein the node is coupled to one of either the drain or source of a transistor. 17. The method of claim 16 , further comprising changing the drive on the gate of the transistor in response to at least one of the first signal or the second signal. 18. The method of claim 12 , wherein coupling the capacitive divider to the node and coupling the resistive divider to the node comprises coupling one of either the resistive divider to the node or coupling the capacitive divider to the node. 19. Circuitry for measuring the voltage across a transistor during voltage transition periods and periods of DC voltage across the transistor, the circuitry comprising: a node coupled to one of either the source or drain of the transistor; a capacitor divider coupled to the node, the capacitor divider having a first output, wherein voltages at the first output are proportional to voltage changes on the node, the capacitive divider having a first capacitor coupled between the node and the first output and at least one second capacitor selectively coupled to the first output; selection circuitry for selectively coupling the at least one second capacitor to the first output in response to the voltage of the first output; a resistive divider coupled to the node, the resistive divider coupled to a second output, wherein voltages at the second output are proportional to DC voltages on the node; first switching circuitry coupled to the capacitor divider for: activating the capacitive divider when first voltages are at the node; and disabling the capacitive divider when the first voltages not at the node; and second switching circuitry coupled to the resistive divider for: activating the resistive divider when second voltages different from the first voltages are at the node; and disabling the resistive divider when the second voltages are not at the node; wherein one of the first switching circuitry or the second switching circuitry activates one of the capacitor divider or the resistive divider at a time. 20. The circuitry of claim 19 , wherein the selection circuitry couples the at least one second capacitor to the first output to achieve a predetermined output at the first output.
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