Gate Leakage Based Low Power Circuits

Patent metadata

Field	Value
Publication number	US-2016112042-A1
Application number	US-201514918384-A
Country	US
Kind code	A1
Filing date	Oct 20, 2015
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A low power voltage divider facility using gate leakage characteristics to divide voltage levels of sub-threshold and near-threshold circuits. The divider comprises a gate leakage based divider facility, and, optionally, a capacitive divider facility.

First claim

What is claimed is:

1 . A voltage divider facility comprising:
a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; and a first capacitive facility coupled between the first and second voltages and adapted to adjust a transient behavior of the first gate-leakage based divider facility.

2 . The voltage divider facility of claim 1 wherein said first gate leakage-based divider facility further comprises:
a first MOS transistor adapted to:
receive said first voltage at a gate terminal of said first MOS transistor; and
output said first divided voltage at a source and a drain terminal of said first MOS transistor;

a second MOS transistor adapted to:
receive said first divided voltage at a gate terminal of said second MOS transistor; and
couple to a second voltage at a source and a drain terminal of said second MOS transistor.

3 . The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are of type NMOS.

4 . The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS devices are of type PMOS.

5 . The voltage divider facility of claim 2 wherein said first MOS transistor is of type NMOS and said second MOS device is of type PMOS.

6 . The voltage divider facility of claim 2 wherein said first MOS transistor is of type PMOS and said second MOS device is of type NMOS.

7 . The voltage divider facility of claim 2 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said first MOS transistor and said second MOS transistor.

8 . The voltage divider facility of claim 2 wherein said first MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.

9 . The voltage divider facility of claim 8 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.

10 . The voltage divider facility of claim 2 wherein said second MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.

11 . The voltage divider facility of claim 10 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.

12 . The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are further characterized as comprising a plurality of parallel connected MOS transistors.

13 . The voltage divider facility of claim 12 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.

14 . The voltage divider facility of claim 1 wherein said first capacitive facility further comprises:
a first capacitor adapted to:
receive said first voltage at a first terminal of said first capacitor; and
output said first divided voltage at a second terminal of said first capacitor;

a second capacitor adapted to:
receive said first divided voltage at a first terminal of said second capacitor; and
couple to a second voltage at a second terminal of said second capacitor.

15 . The voltage divider facility of claim 14 wherein said first capacitor is further characterized as comprising a plurality of parallel connected capacitors.

16 . The voltage divider facility of claim 15 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.

17 . The voltage divider facility of claim 14 wherein said second capacitor is further characterized as comprising a plurality of parallel connected capacitors.

18 . The voltage divider facility of claim 17 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.

19 . The voltage divider facility of claim 14 wherein said first capacitor and said second capacitor are further characterized as comprising a plurality of parallel connected capacitors.

20 . The voltage divider facility of claim 19 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.

21 . An electrical facility comprising a voltage divider facility according to claim 1 .

22 . The electrical facility of claim 21 further characterized as a low dropout regulating facility.

23 . The electrical facility of claim 21 further characterized as an analog to digital conversion facility.

24 . The electrical facility of claim 21 further characterized as a voltage monitor facility.

25 . The electrical facility of claim 24 wherein said voltage monitoring facility further comprises:
a first reference voltage generator adapted to output a first reference voltage; and
a first comparator adapted to:
receive said first divided voltage;
receive said first reference voltage; and
compare said first divided voltage to said first reference voltage, and, in response, to output:
a logic_1 value if said first divided voltage is greater than said first reference voltage; and
a logic _0 value if said first divided voltage is not greater than said first reference voltage.

26 . A voltage divider facility comprising:
a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; wherein said first gate leakage-based divider facility further comprises:
a first MOS transistor adapted to:
receive said first voltage at a gate terminal of said first MOS transistor; and
output said first divided voltage at a source and a drain terminal of said first MOS transistor;

a second MOS transistor adapted to:
receive said first divided voltage at a gate terminal of said second MOS transistor; and
couple to a second voltage at a source and a drain terminal of said second MOS transistor;

wherein said first gate leakage-based divider facility further comprises a plurality of parallel connected MOS transistors; and wherein the first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.

27 . A voltage divider facility comprising:
a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; wherein said first gate leakage-based divider facility further comprises:
a first MOS transistor adapted to:
receive said first voltage at a gate terminal of said first MOS transistor; and
output said first divided voltage at a source and a drain terminal of said first MOS transistor;

a second MOS transistor adapted to:
receive said first divided voltage at a gate terminal of said second MOS transistor; and
couple to a second voltage at a source and a drain terminal of said second MOS transistor; and

wherein said first gate leakage-based divider facility further

Assignees

• Ambiq Micro Inc
• Ambiq Micro Inc

Inventors

• Hanson Scott
• Bartlett Donald Mark
• Lu Yanning

Classifications

• H03L7/181

  a numerical count result being used for locking the loop, the counter counting during fixed time intervals {(H03L7/1806 takes precedence)} · CPC title

• G06F11/3041

  where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title