Airgap spacers

Patent metadata

Field	Value
Publication number	US-10020400-B2
Application number	US-201715668229-A
Country	US
Kind code	B2
Filing date	Aug 3, 2017
Priority date	Feb 18, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
forming one or more dummy gates across one or more semiconductor fins;
forming a lower spacer around the one or more dummy gates that defines a lower portion of a gate region;
forming a sacrificial upper spacer directly above the lower spacer that defines an upper portion of the gate region;
removing the one or more dummy gates to expose the lower portion of the gate region;
forming a gate stack in the gate region;
etching away the sacrificial upper spacer to form an upper spacer opening; and
forming an airgap spacer in the upper spacer opening that comprises a dielectric material that encapsulates an internal void.

2. The method of claim 1 , further comprising forming the one or more semiconductor fins on a substrate.

3. The method of claim 1 , wherein the one or more dummy gates comprise a first dummy gate having a height greater than a height of the one or more semiconductor fins.

4. The method of claim 1 , wherein the one or more dummy gates further comprise a second dummy gate formed over the first dummy gate, and wherein a material of the first dummy gate is different from a material of the second dummy gate.

5. The method of claim 1 , wherein forming the airgap spacer comprises non-conformally depositing a dielectric material that seals off a top opening of the upper spacer opening.

6. The method of claim 1 , wherein the dielectric material comprises a composition of silicon, oxygen, carbon, and nitrogen (SiOCN).

7. The method of claim 1 , wherein the lower spacer comprises a low-k dielectric material.

8. The method of claim 1 , wherein forming the lower spacer comprises:
forming a dummy gate hardmask over the one or more dummy gates;
etching the one or more dummy gates using the dummy gate hardmask as a mask;
depositing low-k dielectric material around the dummy gates after the etching;
removing the dummy gate hardmask and the second dummy gate; and
etching the low-k dielectric material down to a level of the first dummy gate to form the lower spacer.

9. A method for forming a semiconductor device, comprising:
forming one or more dummy gates across one or ore semiconductor fins;
forming a lower spacer around the one or more dummy gates that defines a lower portion of a gate region from a low-k dielectric material;
forming a sacrificial upper spacer directly above the lower spacer that defies an upper portion of the gate region;
removing the one or more dummy gates to expose the lower portion of the gate region;
forming a gate stack in the gate region;
etching away the sacrificial upper spacer to form an upper spacer opening; and
forming an airgap spacer in the upper spacer opening that comprises a dielectric material formed from a composition of silicon, oxygen, carbon, and nitrogen (SiOCN) that encapsulates an internal void.

10. The method of claim 9 , further comprising forming the one or more semiconductor tins on a substrate.

11. The method of claim 9 , wherein the one or more dummy gates comprise a first dummy gate having a height greater than a height of the one or more semiconductor fins.

12. The method of claim 9 , wherein the one or more dummy gates further comprise a second dummy gate formed over the first dummy gate, and wherein a material of the first dummy gate is different from a material of the second dummy gate.

13. The method of claim 9 , wherein forming the airgap spacer comprises non-conformally depositing a dielectric material that seals off a top opening of the upper spacer opening.

14. The method of claim 9 , wherein forming the lower spacer comprises:
forming a dummy gate hardmask over the one or more dummy gates;
etching the one or more dummy gates using the dummy gate hardmask as a mask;
depositing the low-k dielectric material around the dummy gates after the etching;
removing the dummy gate hardmask and the second dummy gate; and
etching the low-k dielectric material down to a level of the first dummy gate to form the lower spacer.

15. A semiconductor device, comprising:
a semiconductor fin formed on a substrate;
a gate stack formed across and over a channel region of the semiconductor fin; and
an airgap spacer formed around the gate stack, the airgap spacer comprising a dielectric material that encapsulates an internal void.

16. The semiconductor device of claim 15 , further comprising extended source and drain regions on the semiconductor fin.

17. The semiconductor device of claim 15 , further comprising a lower spacer formed over the semiconductor fin and around the gate stack, directly underneath the airgap spacer.

18. The semiconductor device of claim 17 , wherein the lower spacer comprises a low-k dielectric material.

19. The semiconductor device of claim 15 , wherein the dielectric material comprises a composition of silicon, oxygen, carbon, and nitrogen (SiOCN).

20. The semiconductor device of claim 15 , wherein a lowest point of the airgap spacer is higher than a highest point of the semiconductor fin.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Liu Zuoguang
• Yeung Chun W

Classifications

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L21/0214

  Electricity · mapped topic