Tungsten gates for non-planar transistors

Patent metadata

Field	Value
Publication number	US-10020375-B2
Application number	US-201715726609-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Sep 30, 2011
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a fin, wherein the fin comprises silicon;
a transistor gate on the fin, wherein the transistor gate comprises:
a first gate dielectric on the fin, wherein the gate dielectric comprises silicon and oxygen;
a second gate dielectric on the first gate dielectric, wherein the second gate dielectric comprises hafnium and oxygen;
an NMOS gate electrode on the second gate dielectric, wherein the NMOS gate electrode comprises:
a first layer on the second gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon;
a second layer on the first layer, wherein the second layer comprises titanium; and
a third layer on the second layer, wherein the third layer comprises tungsten;

a first sidewall on one side of the NMOS gate electrode; and
a second sidewall on another side of the NMOS gate electrode that opposes the first sidewall;

a source region comprising an n-type dopant, wherein the source region is proximate the first sidewall;
a drain region comprising an n-type dopant, wherein the drain region is proximate the second sidewall;
a first contact coupled to the source region, wherein the first contact comprises tungsten; and
a second contact coupled to the drain region, wherein the second contact comprises tungsten.

2. The integrated circuit (IC) structure of claim 1 , further comprising a capping structure over the NMOS gate electrode.

3. The integrated circuit (IC) structure of claim 2 , wherein the capping structure is disposed adjacent the NMOS metal gate electrode and between the first sidewall and the second sidewall.

4. The integrated circuit (IC) structure of claim 2 , wherein the capping structure comprises silicon and nitrogen.

5. The integrated circuit (IC) structure of claim 4 , wherein the capping structure comprises silicon nitride.

6. The integrated circuit (IC) structure of claim 1 , further comprising a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen.

7. The integrated circuit (IC) structure of claim 6 , wherein the dielectric layer comprises silicon oxide.

8. The integrated circuit (IC) structure of claim 6 , wherein the first contact and the second contact extend through the dielectric layer.

9. The integrated circuit (IC) structure of claim 1 , wherein the first layer comprises a conformal layer.

10. The integrated circuit (IC) structure of claim 1 , wherein the second layer comprises a conformal layer.

11. A method of fabricating an integrated circuit (IC) structure, comprising:
forming a fin, wherein the fin comprises silicon;
forming a transistor gate on the fin, wherein forming the transistor gate comprises:
forming a first gate dielectric on the fin, wherein the gate dielectric comprises silicon and oxygen;
forming a second gate dielectric on the first gate dielectric, wherein the second gate dielectric comprises hafnium and oxygen;
forming an NMOS gate electrode on the second gate dielectric, wherein the NMOS gate electrode comprises:
forming a first layer on the second gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon;
forming a second layer on the first layer, wherein the second layer comprises titanium; and
forming a third layer on the second layer, wherein the third layer comprises tungsten;

forming a first sidewall on one side of the NMOS gate electrode; and
forming a second sidewall on another side of the NMOS gate electrode that opposes the first sidewall;

forming a source region comprising an n-type dopant, wherein the source region is proximate the first sidewall;
forming a drain region comprising an n-type dopant, wherein the drain region is proximate the second sidewall;
forming a first contact coupled to the source region, wherein the first contact comprises tungsten; and
forming a second contact coupled to the drain region, wherein the second contact comprises tungsten.

12. The method of claim 11 , further comprising forming a capping structure over the NMOS gate electrode.

13. The method of claim 12 , wherein forming the capping structure comprises forming the capping structure adjacent the NMOS metal gate electrode and between the first sidewall and the second sidewall.

14. The method of claim 12 , wherein forming the capping structure comprises forming capping structure comprising silicon and nitrogen.

15. The method of claim 14 , wherein forming the capping structure comprises forming a silicon nitride capping structure.

16. The method of claim 11 , further comprising forming a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen.

17. The method of claim 16 , wherein forming the dielectric layer comprises forming a silicon oxide dielectric layer.

18. The method of claim 16 , wherein forming the first contact comprises forming the first contract extending through the dielectric layer and wherein forming the second contact comprises forming the second contact extending through the dielectric layer.

19. The method of claim 11 , wherein forming the first layer comprises forming a conformal first layer.

20. The method of claim 11 , wherein forming the second layer comprises forming a conformal second layer.

Assignees

• Intel Corp

Inventors

• Pradhan Sameer S
• Bergstrom Daniel B
• Chun Jin-Sung
• Chiu Julia

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• C23C14/0635

  Carbides · CPC title

• H01L21/823821

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic