Tape for electronic devices with reinforced lead crack

US10020248B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10020248-B2
Application numberUS-201615153970-A
CountryUS
Kind codeB2
Filing dateMay 13, 2016
Priority dateJan 31, 2011
Publication dateJul 10, 2018
Grant dateJul 10, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion, the problem of occurrence of cracks along a width of a narrow wiring can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a cutting portion formed on one of the first lead and the second lead wherein the cutting portion is formed within a resin application portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A tape for electronic devices comprising: a dielectric substrate; a resin application portion corresponding to a chip mounting portion formed on the dielectric substrate; an electronic device chip mounted on the chip mounting portion, and resin for burying the electronic device chip in the resin application portion; a first lead having a plurality of first lead patterns and disposed on the dielectric substrate and connected to a terminal outside the dielectric substrate; and a second lead having a plurality of second lead patterns and disposed on the resin application portion of the dielectric substrate and connected to the electronic device chip; wherein the second lead includes a cutting portion disposed in the resin application portion, wherein the cutting portion connects the first lead and the second lead in a cutting form; wherein the cutting portion includes a plurality of connecting patterns connecting the plurality of first lead patterns and the plurality of second lead patterns, respectively; wherein the plurality of connecting patterns includes a first connecting pattern, a second connecting pattern, and a third connecting pattern; wherein the first connecting pattern has a first portion having a first angle of inclination with respect to the plurality of first lead patterns and a second portion extended in a longitudinal direction of the plurality of first lead patterns, wherein the second connecting pattern has a third portion having a second angle of inclination with respect to the plurality of first lead patterns and a fourth portion extended in a longitudinal direction of the plurality of first lead patterns, wherein the third connecting pattern is only straightly formed for directly connecting the first lead and the second lead in the longitudinal direction of the plurality of first lead patterns, wherein the first angle of inclination is different from the second angle of inclination, wherein the third connecting pattern is positioned outermost of the plurality of connecting patterns in a direction transverse to the longitudinal direction of the plurality of first lead patterns, wherein each of the plurality of second lead patterns has a width smaller than a width of each of the plurality of first lead patterns, wherein the number of the plurality of first lead patterns is different from the number of the plurality of second lead patterns, wherein the second portion of the first connecting pattern has a plurality of first sub-connecting patterns branching from one first lead pattern of the plurality of first lead patterns, wherein the fourth portion of the second connecting pattern has a plurality of second sub-connecting patterns branching from another first lead pattern of the plurality of first lead patterns, wherein a position of an end of each of the plurality of first sub-connecting patterns is different from each other, and wherein a position of an end of each of the plurality of second sub-connecting patterns is different from each other. 2. The tape for electronic devices of claim 1 , wherein a width of the first lead and a width of the second lead are different from each other. 3. The tape for electronic devices of claim 2 , wherein a pattern width of the first lead is wider than that of the second lead. 4. The tape for electronic devices of claim 1 , wherein the resin comprises a potting material having viscosity. 5. The tape for electronic devices of claim 1 , wherein the resin comprises epoxy. 6. The tape for electronic devices of claim 5 , wherein the resin further comprises a curing material or an inorganic filler. 7. The tape for electronic devices of claim 1 , wherein the dielectric substrate comprises a polyimide film. 8. The tape for electronic devices of claim 1 , wherein a plating treatment layer having a material different from those of the first lead and the second lead is disposed on the first lead and the second lead. 9. The tape for electronic devices of claim 8 , wherein the plating treatment layer is made of one material selected from the group consisting of Cu, Ni, Pd, Au, Sn, Ag and Co, and binary and ternary alloys thereof. 10. The tape for electronic devices of claim 9 , wherein the plating treatment layer has a multi-layer structure.

Assignees

Inventors

Classifications

  • Tape-automated bond [TAB] connectors · CPC title

  • Connecting of TAB connectors · CPC title

  • the encapsulations having cavities other than that occupied by chips · CPC title

  • of metallic layers on leadframes · CPC title

  • H10W70/453Primary

    comprising flexible metallic tapes · CPC title

Patent family

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External sources

Frequently asked questions

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What does patent US10020248B2 cover?
Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion, the problem of occurrence of cracks along a width of a narrow wiring can be av…
Who is the assignee on this patent?
Lg Innotek Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/453. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).