Method for forming a semiconductor device and a semiconductor device

Patent metadata

Field	Value
Publication number	US-10020226-B2
Application number	US-201715645402-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Jul 31, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of semiconductor chips each comprising:
a semiconductor body having a first side and a second side opposite the first side and comprising a wide band-gap semiconductor material, the wide band-gap semiconductor material comprising silicon carbide or gallium nitride;
a graphite substrate bonded to the second side of the semiconductor body by a ceramic-forming polymer precursor and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate;
a back-side metallization arranged in the opening of the graphite substrate, surrounded by the graphite substrate, and electrically contacting the area of the second side; and
a front-side metallization formed on the first side of the semiconductor body and electrically contacting the semiconductor body;

a foil attached to each of the plurality of semiconductor chips such that the graphite substrate of each of the plurality of semiconductor chips is arranged between at least a portion of the foil and the semiconductor body of each of the plurality of semiconductor chips;
a plurality of separation trenches, each of the plurality of separation trenches separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips and extending vertically from a top surface of the semiconductor device through at least a portion of the foil; and
wherein:
the graphite substrate surrounds the semiconductor body when seen from above; or
the semiconductor body is completely arranged within the graphite substrate when seen from above.

2. A semiconductor device comprising:
a plurality of semiconductor chips each comprising:
a semiconductor body having a first side and a second side opposite the first side and comprising a wide band-gap semiconductor material;
a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate;
a back-side metallization arranged in the opening of the graphite substrate, surrounded by the graphite substrate, and electrically contacting the area of the second side; and
a front-side metallization formed on the first side of the semiconductor body and electrically contacting the semiconductor body;

a plurality of separation trenches, each of the plurality of separation trenches separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips; and
a foil attached to each of the plurality of semiconductor chips such that the graphite substrate of each of the plurality of semiconductor chips is arranged between at least a portion of the foil and the semiconductor body of each of the plurality of semiconductor chips.

3. A semiconductor device comprising:
a plurality of semiconductor chips each comprising:
a semiconductor body having a first side and a second side opposite the first side;
a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate;
a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side; and

a plurality of separation trenches, each of the plurality of separation trenches separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.

4. The semiconductor device of claim 3 , wherein the graphite substrate surrounds the semiconductor body when seen from above.

5. The semiconductor device of claim 3 , wherein the semiconductor body is completely arranged within the graphite substrate when seen from above.

6. The semiconductor device of claim 3 , wherein the semiconductor body comprises a wide band-gap semiconductor material.

7. The semiconductor device of claim 6 , wherein the wide band-gap semiconductor material is silicon carbide or gallium nitride.

8. The semiconductor device of claim 3 , further comprising a foil attached to each of the plurality of semiconductor chips such that the graphite substrate of each of the plurality of semiconductor chips is arranged between at least a portion of the foil and the semiconductor body of each of the plurality of semiconductor chips.

9. The semiconductor device of claim 3 , further comprising a seed layer formed on a side of the graphite substrate, at least a portion of the seed layer arranged between the graphite substrate and the back-side metallization.

10. The semiconductor device of claim 3 , further comprising a front-side metallization formed on the first side of the semiconductor body and electrically contacting the semiconductor body.

11. The semiconductor device of claim 3 , wherein the semiconductor body is formed from a split layer and an epitaxial layer.

12. The semiconductor device of claim 1 , wherein a doping concentration of the split layer is higher than a doping concentration of the epitaxial layer.

13. The semiconductor device of claim 3 , wherein the semiconductor body has a thickness of less than 100 μm.

14. The semiconductor device of claim 3 , wherein each of the plurality of separation trenches extends vertically from the first side of the semiconductor body through at least a portion of the graphite substrate.

15. The semiconductor device of claim 3 , wherein each of the plurality of separation trenches extends vertically from the first side of the semiconductor body through at least a portion of the foil.

16. The semiconductor device of claim 3 , wherein:
the semiconductor device is a MOSFET device; and
the back-side metallization is a drain of the MOSFET device.

17. The semiconductor device of claim 3 , wherein:
the semiconductor device is a power diode; and
the back-side metallization is a cathode of the power diode.

18. The semiconductor device of claim 3 , wherein a first width of a first portion of each of the plurality of separation trenches is greater than a second width of a second portion of each of the plurality of separation trenches.

19. The semiconductor device of claim 18 , wherein:
the first portion of each of the plurality of separation trenches is arranged between the semiconductor body of the one of the plurality of semiconductor chips and the semiconductor body of the adjacent one of the plurality of semiconductor chips; and
the second portion of each of the plurality of separation trenches is arranged between the graphite substrate of the one of the plurality of semiconductor chips and the graphite substrate of the adjacent one of the plurality of semiconductor chips.

20. The semiconductor device of claim 3 , wherein an extension of the back-side metallization in a vertical direction is between 500 nm and 200 μm.

Assignees

• Infineon Technologies Ag

Inventors

• Rupp Roland
• Lehnert Wolfgang
• Santos Rodriguez Francisco Javier
• Schulze Hans-Joachim

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title