Memory module, computing system having the same, and method for testing tag error thereof

Patent metadata

Field	Value
Publication number	US-10019367-B2
Application number	US-201715479795-A
Country	US
Kind code	B2
Filing date	Apr 5, 2017
Priority date	Dec 14, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

First claim

What is claimed is:

1. A method of a computing system that comprises at least one nonvolatile memory, a memory module performing a cache function of the nonvolatile memory and comprising cache dynamic random access memories (DRAMs), and a processor controlling the nonvolatile memory and the memory module, the method comprising:
outputting, at the processor, a command and an address to the memory module;
receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the cache DRAMs of the memory module, from the memory module;
determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting; and
outputting, at the processor, the determined cache hit/miss to the memory module.

2. The method of claim 1 , wherein the command is a read command,
the method further comprising:
receiving, at the processor, data from the memory module when the cache hit/miss information indicates a cache hit.

3. The method of claim 1 , wherein the command is a read command, and
the method further comprising:
reading data from the nonvolatile memory based on the address when the cache hit/miss information indicates a cache miss; and
receiving, at the processor, the read data through the memory module.

4. The method of claim 1 ,
wherein each of the cache DRAMs comprises a tag comparator that compares a tag corresponding to the address and a stored tag and outputs a match/unmatch bit in response to the comparison.

5. The method of claim 4 , further comprising:
determining whether a match bit count associated with the match/unmatch bits is greater than “0” and an unmatch bit count associated with the match/unmatch bits is greater than “0”;
determining that a tag error is absent, when the match bit count is “0” or the unmatch bit count is “0”; and
determining that a tag error is present, when the match bit count is greater than “0” and the unmatch bit count is greater than “0”.

6. The method of claim 5 , further comprising:
accessing a first one of the cache DRAMs, in which a tag error is present, in a write operation or a read operation by using location information of a second one of the cache DRAMs in which a tag error is absent.

7. The method of claim 5 , further comprising:
correcting a tag error of a first one of the cache DRAMs, in which the tag error is present, by using location information and a parity of a second one of the cache DRAMs in which a tag error is absent.

8. The method of claim 7 , further comprising:
buffering, at the memory module, data in a write operation until a tag error is detected and corrected; and
writing the buffered data after the tag error is corrected.

9. A tag error test method of a computing system that comprises at least one nonvolatile memory, a memory module performing a cache function of the nonvolatile memory, and a processor controlling the nonvolatile memory and the memory module, the method comprising:
generating, at each of a plurality of cache DRAMs of the memory module, a match/unmatch bit as a result of comparing a tag corresponding to an address and a tag stored in a respective one of the plurality of cache DRAMs;
determining whether a match bit count is greater than “0” and an unmatch bit count is greater than “0”; and
determining a cache hit/miss from the match/unmatch bits through majority voting when the match bit count is greater than “0” and the unmatch bit count is greater than “0”.

10. The method of claim 9 , further comprising:
determining, at a memory controller of the processor, whether the match bit count is greater than “0” and the unmatch bit count is greater than “0”.

11. The method of claim 9 , further comprising:
determining, at the memory module, whether the match bit count is greater than “0” and the unmatch bit count is greater than “0”.

12. The method of claim 9 , further comprising:
determining that a tag error is absent when the match bit count is “0” or the unmatch bit count is “0”.

13. The method of claim 9 , further comprising:
determining that a tag error is present when the match bit count is greater than “0” and the unmatch bit count is greater than “0”; and
correcting, when the tag error is present, an error of the tag stored in one of the plurality of cache DRAMs in which the tag error is present by using location information of a second one of the plurality of cache DRAMs in which a tag error is absent.

14. A method, comprising:
receiving a command and an address at a cache memory module, the cache memory module comprising a plurality of cache memory blocks;
determining cache hit/miss information based on an input tag associated with the address and a plurality of tags stored in the plurality of cache memory blocks, respectively;
determining that one of the plurality of tags is in error due to being different than other ones of the plurality of tags;
determining whether the one of the plurality of tags that is different is correctable; and
correcting the one of the plurality of tags that is different from the other ones of the plurality of tags at the cache memory module when the one of the plurality of tags that is different is determined to be correctable.

15. The method of claim 14 , further comprising:
sending information to a memory controller indicating that the one of the plurality of tags was determined not to be correctable.

16. The method of claim 14 , wherein each of the plurality of cache memory blocks are configured to store metadata indicating whether cache data stored therein are valid; and
wherein the method further comprises:
determining that the metadata in one of the plurality of cache memory blocks contains an error; and
correcting the error in the metadata in the one of the plurality of cache memory blocks at the cache memory device.

17. The method of claim 16 , wherein each of the plurality of cache memory blocks are configured to store parity information associated with the respective metadata and parity information associated with respective ones of the plurality of tags;
wherein correcting the one of the plurality of tags comprises correcting the one of the plurality of tags using the respective parity information associated with the one of the plurality of tags; and
wherein correcting the error in the metadata comprises correcting the error in the metadata in the one of the plurality of cache memory blocks using the respective parity information associated with the metadata in the one of the plurality of cache memory blocks.

18. The method of claim 14 , further comprising:
accessing the one of the plurality of cache memory blocks that stores the one of the plurality of tags that is different based on location information obtained from another one of the plurality of cache memory blocks.

19. The method of claim 14 , wherein the cache memory module comprises a registered connective device; and
wherein receiving the command and the address at the cache memory module comprises receiving the command and the address at the registered connective device.

20. The method of claim 19 , further comprising:
controlling the one of the plurality of cache memory blocks that stores the one of the plurality of tags that is different based on a predetermined policy using the registered connective device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• O Seongil
• Kim Chankyung
• Son Jongpil

Classifications

• G06F12/0846 Primary

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F12/0884

  Parallel mode, e.g. in parallel with main memory or CPU · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/0844

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title