Address Range Based Memory Hints for Prefetcher, Cache and Memory Controller
US-2024385966-A1 · Nov 21, 2024 · US
US8935481B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935481-B2 |
| Application number | US-201213656108-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 19, 2012 |
| Priority date | Oct 19, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Official abstract text for this publication.
Aspects of the present disclosure disclose systems and methods for managing a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. Any data stored in the level-two cache may be stored in a particular version or format of data known as “raw” data, in contrast to storing the data in a “cooked” version, as is typically stored in a level-one cache.
Opening claim text (preview).
What is claimed is: 1. A method for providing raw data comprising: storing, for each data block of a plurality of data blocks, a raw version of the data block and a cooked version of the data block in a level-one cache of a file system; determining whether a first data block of the plurality of data blocks is a candidate for a level-two cache; and storing the raw version of the first data block into the level-two cache of the file system when the first data block is the candid…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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