Calculation control indicator cache

Patent metadata

Field	Value
Publication number	US-10019230-B2
Application number	US-201514748956-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jul 2, 2014
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

An arithmetic operation is performed using a first instruction execution unit to generate an intermediate result vector and a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The intermediate result vector and the plurality of calculation control indicators are stored in memory external to the instruction execution unit, and later read by a second instruction execution unit to complete the arithmetic operation.

First claim

The invention claimed is:

1. A method in a microprocessor of performing an arithmetic operation, the method comprising:
using an instruction execution unit to generate an intermediate result vector and a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed; and
storing the intermediate result vector and the plurality of calculation control indicators in memory external to the instruction execution unit.

2. The method of claim 1 , further comprising loading the intermediate result vector and the plurality of calculation control indicators from memory; and performing calculations on the intermediate result vector in accordance with the calculation control indicators to generate a final result.

3. The method of claim 1 , wherein the arithmetic operation is a fused floating point multiply-accumulate operation whose operands include a multiplicand, a multiplier, and an accumulator, and wherein the intermediate result vector is a sum of at least partial products of the multiplicand and the multiplier.

4. The method of claim 1 , wherein the arithmetic operation is a fused operation involving at least one multiplication and at least one accumulation.

5. The method of claim 1 , wherein the arithmetic operation is a compound arithmetic operation involving two or more arithmetic operators.

6. The method of claim 5 , further comprising splitting the compound arithmetic operation into a first arithmetic operation using a first arithmetic operand and a second arithmetic operation using a second arithmetic operand.

7. The method of claim 6 , wherein the calculation control indicators indicate how the second arithmetic operation should proceed.

8. The method of claim 5 , wherein the compound arithmetic operation is a sequential arithmetic operation.

9. The method of claim 5 , wherein the calculation control indicators provide information regarding how much of the compound arithmetic operation has been completed in generating the intermediate result vector.

10. The method of claim 5 , wherein the calculation control indicators provide information regarding whether the first arithmetic operation resulted in an underflow or overflow condition.

11. The method of claim 5 , further comprising storing the intermediate result vector in a storage format that, when considered in isolation from the calculation control indicators, provides fewer bits than necessary to consistently generate a representation of a result of the compound arithmetic operation that is indistinguishable from a result that would be generated by an infinitely precise calculation of the compound arithmetic operation subsequently reduced in significance to a target data size; but wherein the storage format, in combination with the plurality of calculation control indicators, provides sufficient information to consistently generate a result of the compound arithmetic operation that is indistinguishable from the result that would be generated by an infinitely precise calculation of the compound arithmetic operation subsequently reduced in significance to a target data size.

12. A method in a microprocessor of performing a rounding operation, the method comprising:
a first one of a plurality of instruction execution units generating an unrounded result;
storing at least one rounding indicator into a rounding cache external to the plurality of instruction execution units;
supplying the unrounded result and the at least one rounding indicator from the rounding cache to a second one of the plurality of instruction execution units; and
the second instruction execution unit generating a final rounded result using at least the unrounded result and the at least one rounding indicator.

13. The method of claim 12 , further comprising storing the unrounded result in a general purpose storage that is distinct from the rounding cache.

14. The method of claim 12 , further comprising transferring the one rounding indicator from the first instruction unit to the rounding cache through a data path that is separate from a result bus coupling the plurality of instruction execution units to a general purpose storage.

15. A method in a microprocessor of performing an arithmetic operation, the method comprising:
using a first instruction execution unit, generating an intermediate result vector;
concomitantly generating a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed;
forwarding the intermediate result vector and the plurality of calculation control indicators to a second instruction execution unit; and
using the second instruction execution unit, generating the final result and complete the arithmetic operation in accordance with the calculation control indicators.

16. The method of claim 15 , wherein the arithmetic operation is a compound arithmetic operation.

17. The method of claim 16 , wherein the compound arithmetic operation is of a type in which only a single rounding is permitted to generate the final result.

18. The method of claim 15 , wherein the arithmetic operation is a fused multiply-accumulate operation.

19. The method of claim 18 , wherein the intermediate result vector is an unrounded result of a portion of the multiply-accumulate operation and the calculation control indicators include rounding indicators for generating a final rounded result of the multiply-accumulate operation.

20. The method of claim 15 , wherein forwarding of the intermediate result vector is done via a result bus and forwarding of the calculation control characters is done via a data path that is distinct from the result bus.

Assignees

• Via Alliance Semiconductor Co Ltd
• Via Alliance Semiconductor Co Ltd

Inventors

• Elmer Thomas

Classifications

• G06F7/499

  Denomination or exception handling, e.g. rounding or overflow · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F7/49915

  Mantissa overflow or underflow in handling floating-point numbers · CPC title

• G06F7/485

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title