Integrated circuit having eye opening monitor and serializer/deserializer device

Patent metadata

Field	Value
Publication number	US-10014907-B2
Application number	US-201514957969-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Jan 20, 2015
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An integrated circuit having an eye opening monitor (EOM) is provided. The integrated circuit may include: an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit, wherein the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages, and wherein the comparator divides the target reference voltages from the first and second input voltages respectively by varying a driving capability according to size information data, and compares the first and second input voltages with divided target reference voltages.

First claim

What is claimed is:

1. An integrated circuit comprising:
an internal circuit; and
an eye opening monitor (EOM) configured to measure an eye diagram of a predetermined point of the internal circuit,
wherein the EOM comprises a comparator configured to receive a first parent reference voltage and a second parent reference voltage and a first input voltage and a second input voltage from the internal circuit, and to compare the first input voltage and the second input voltage with target reference voltages that are obtained by dividing the first parent reference voltage and the second parent reference voltage according to a driving capability of the comparator,
wherein the driving capability of the comparator is varied according to size information data, and values of the target reference voltages are changed according to the varied driving capability.

2. The integrated circuit of claim 1 , wherein the EOM further comprises a digital to analog converter (DAC) configured to receive reference voltage data and to output the first parent reference voltage and the second parent reference voltage to the comparator.

3. The integrated circuit of claim 1 , further comprising:
a sensing amplifier configured to sample and amplify an output value of the comparator in response to a clock.

4. The integrated circuit of claim 3 , further comprising:
a counter configured to perform counting in response to an output value of the sensing amplifier.

5. The integrated circuit of claim 3 , further comprising:
a phase locked loop (PLL) configured to receive a reference clock and to generate the clock,
wherein the PLL comprises a phase interpolator (PI) configured to shift a phase of the clock in response to a selection bit.

6. The integrated circuit of claim 1 , wherein the comparator comprises:
a main branch configured to receive the first input voltage and the second input voltage respectively at a first node and a second node; and
a plurality of reference branches, each of which configured to provide the first parent reference voltage and the second parent reference voltage respectively to the first node and the second node.

7. The integrated circuit of claim 6 , wherein each of the plurality of reference branches is enabled in response to the size information data.

8. The integrated circuit of claim 7 , wherein the main branch and the plurality of reference branches are configured such that an amount of current which flows in the main branch is identical to an amount of current which flows in the enabled reference branches among the plurality of reference branches.

9. The integrated circuit of claim 6 , wherein at least two reference branches among the plurality of reference branches are implemented with transistors of different sizes.

10. The integrated circuit of claim 1 , wherein the comparator comprises a first comparator and a second comparator,
wherein each of the first comparator and the second comparator comprises:
a main branch configured to receive the first input voltage and the second input voltage respectively at a first node and a second node, and
a plurality of reference branches, each of which configured to provide the first parent reference voltage and the second parent reference voltage respectively to the first node and the second node,
wherein each of the plurality of reference branches is enabled in response to the size information data, and
wherein the first parent reference voltage and the second parent reference voltage input to the plurality of reference branches of the first comparator and the first parent reference voltage and the second parent reference voltage input to the plurality of reference branches of the second comparator are complementary with each other.

11. The integrated circuit of claim 10 , wherein each of the first comparator and the second comparator comprises:
a first multiplexer configured to select one of a supply voltage, a ground voltage, the first parent reference voltage, and the second parent reference voltage, and to provide the selected voltage to the plurality of reference branches; and
a second multiplexer configured to select one of the supply voltage, the ground voltage, the first parent reference voltage, and the second parent reference voltage, and to provide the selected voltage to the plurality of reference branches, and
wherein the voltage selected by the first multiplexer and the voltage selected by the second multiplexer are complementary with each other.

12. The integrated circuit of claim 10 , further comprising:
a first sensing amplifier configured to sample and amplify an output value of the first comparator in response to a clock; and
a second sensing amplifier configured to sample and amplify an output value of the second comparator in response to the clock.

13. The integrated circuit of claim 12 , further comprising:
a logic circuit configured to exclusive OR (XOR) compute an output value of the first sensing amplifier and an output value of the second sensing amplifier; and
a counter configured to count an output value of the logic circuit until the output value of the logic circuit is input as a signal with a level of a predetermined state.

14. The integrated circuit of claim 12 , further comprising:
a phase locked loop (PLL) configured to receive a reference clock and generate the clock,
wherein the PLL comprises a phase interpolator (PI) configured to shift a phase of the clock in response to a selection bit.

15. An integrated circuit comprising:
a continuous time linear equalizer (CTLE) configured to amplify serial data signals;
a sampler configured to sample a first input voltage and a second input voltage output from the CTLE; and
an eye opening monitor (EOM) configured to measure an eye diagram of the first input voltage and the second input voltage, and
wherein the EOM comprises:
a digital to analog converter (DAC) configured to receive reference voltage data and output a first parent reference voltage and a second parent reference voltage; and
a comparator configured to receive the first parent reference voltage and the second parent reference voltage and the first input voltage and the second input voltage output from the CTLE, and to compare the first input voltage and the second input voltage with target reference voltages that are obtained by dividing the first parent reference voltage and the second parent reference voltage according to a driving capability of the comparator,
wherein the driving capability of the comparator is varied according to size information data, and values of the target reference voltages are changed according to the varied driving capability.

16. The integrated circuit of claim 15 , further comprising:
a decision feedback equalizer (DFE) configured to connect between the CTLE and the sampler.

17. The integrated circuit of claim 16 , further comprising:
a first buffer configured to output voltages between the CTLE and the DFE as input voltages of the EOM in response to a first enable signal; and
a second buffer configured to output voltages between the DFE and the sampler as input voltages of the EOM in response to a second enable signal,
wherein the first enable signal and the second enable signal are complementary with each other.

18. The integrated circuit of claim 16 , further comprising:
a clock and data recovery (CDR) circuit configured to reproduce data and a clock output from the sampler.

19. A serializer/deserializer (SERDES) device comprising:
a receiver configured to receive recepti

Assignees

• Choi Hwang Ho
• Kim Duho
• Park Jaehyun
• Seong Chang Kyung
• Samsung Electronics Co Ltd

Inventors

• Choi Hwang Ho
• Kim Duho
• Park Jaehyun
• Seong Chang-Kyung

Classifications

• H04B3/46 Primary

  Monitoring; Testing · CPC title

• G01R31/3171

  BER [Bit Error Rate] test · CPC title

• G11C29/702

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title

• G11C29/50004

  of threshold voltage · CPC title