Semiconductor device having a defined oxygen concentration

Patent metadata

Field	Value
Publication number	US-10014400-B2
Application number	US-201715650504-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Oct 9, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A semiconductor device includes: a semiconductor substrate having a first side, a second side opposite the first side, and a thickness; at least one semiconductor component integrated in the semiconductor substrate; a first metallization at the first side of the semiconductor substrate; and a second metallization at the second side of the semiconductor substrate. The semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side. The global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a first side, a second side opposite the first side, and a thickness;
at least one semiconductor component integrated in the semiconductor substrate;
a first metallization at the first side of the semiconductor substrate;
a second metallization at the second side of the semiconductor substrate;
wherein the semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side,
wherein the global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein the global maximum is at least 5-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.

3. The semiconductor device of claim 1 , wherein the global maximum of the oxygen concentration is less than 5*10 17 /cm 3 .

4. The semiconductor device of claim 1 , wherein the global maximum of the oxygen concentration is equal to or less than 3*10 17 /cm 3 .

5. The semiconductor device of claim 1 , wherein the semiconductor device is a bipolar device.

6. The semiconductor device of claim 1 , wherein the semiconductor device is a MOSFET.

7. The semiconductor device of claim 1 , wherein the thickness of the monocrystalline silicon substrate is less than 400 μm.

8. The semiconductor device of claim 1 , wherein the semiconductor substrate is a monocrystalline silicon substrate.

9. The semiconductor device of claim 1 , wherein the semiconductor device is a bipolar power semiconductor device and includes an IGBT.

10. The semiconductor device of claim 9 , wherein the semiconductor device comprises a plurality of field-effect structures each forming a respective transistor cell of the IGBT.

11. The semiconductor device of claim 1 , wherein the semiconductor device is a bipolar power semiconductor device and includes a diode.

12. The semiconductor device of claim 1 , wherein the semiconductor device is a unipolar power semiconductor device and includes a power MOSFET.

13. The semiconductor device of claim 1 , wherein the semiconductor device is a three-terminal power semiconductor device.

14. The semiconductor device of claim 1 , wherein the semiconductor device is a two-terminal power semiconductor device.

15. The semiconductor device of claim 1 , further comprising:
gate electrodes arranged in trenches formed in the semiconductor substrate;
gate dielectrics electrically insulating the gate electrodes from the semiconductor substrate; and
mesa regions formed between the trenches.

16. The semiconductor device of claim 15 , further comprising:
a source region of a first conductivity type arranged in the mesa regions at the first side of the semiconductor substrate;
a body region of a second conductivity type arranged in the mesa regions below the source region;
a drift region of the first conductivity type arranged below the body region;
a drain region of the first conductivity type or an emitter region of the second conductivity type arranged below the drift region.

17. The semiconductor device of claim 16 , further comprising:
a field stop region of the first conductivity type arranged between the drift region and the drain region or the emitter region.

18. The semiconductor device of claim 17 , wherein the oxygen concentration in the field stop region is lower than in the drift region.

19. The semiconductor device of claim 16 , wherein the oxygen concentration in the source region is lower than in the drift region.

20. The semiconductor device of claim 16 , wherein the oxygen concentration in the drain region or the emitter region is lower than in the drift region.

Assignees

• Infineon Technologies Ag

Inventors

• Oefner Helmut
• Caspary Nico
• Momeni Mohammad
• Ploss Reinhard
• Santos Rodriguez Francisco Javier
• Schulze Hans-Joachim

Classifications

• H10P95/902

  for the formation of PN junctions without addition of impurities · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D64/01352

  with sacrificial oxide · CPC title