Method of manufacturing non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9257304-B2
Application number	US-201414523183-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Feb 17, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method for manufacturing a non-volatile memory includes depositing a first conductive film and a protective film on a substrate including a logic area and a cell area, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film to pattern the hard mask layer, using the patterned hard mask layer to form a logic gate on the logic area, exposing a surface of the first conductive film in the cell area and forming a control gate on the cell area.

First claim

What is claimed is:

1. A method of manufacturing a non-volatile memory device, comprising:
providing a substrate comprising a logic area and a cell area;
forming a floating gate on the cell area;
depositing a first conductive film and a protective film on the substrate;
patterning the protective film;
depositing a hard mask layer on the first conductive film and the patterned protective film;
patterning the hard mask layer;
forming a logic gate on the logic area using the patterned hard mask layer;
exposing a surface of the first conductive film in the cell area; and
forming a control gate on the cell area.

2. The method of manufacturing of claim 1 , wherein the patterning of the protective film comprises:
forming a first mask pattern on an upper portion of the floating gate; and
removing the protective film exposed by the first mask pattern, the first mask pattern corresponding to an etching mask.

3. The method of manufacturing of claim 2 , wherein the patterning of the hard mask layer comprises:
forming a second mask pattern for etching the hard mask layer;
patterning the hard mask layer by the second mask pattern, the second mask pattern corresponding to the etching mask;
removing the second mask pattern; and
forming a third mask pattern on an upper portion of the floating gate.

4. The method of manufacturing of claim 1 , wherein the exposing of the surface of the first conductive film in the cell area comprises:
forming a fourth mask pattern exposing the hard mask layer in the upper portion of the floating gate; and
sequentially etching the hard mask layer and the protective layer of the upper portion of the floating gate.

5. The method of manufacturing of claim 1 , wherein a height of the control gate is greater than that of the logic gate.

6. The method of manufacturing of claim 1 , wherein the control gate is located beside the floating gate.

7. The method of manufacturing of claim 1 , wherein the protective film comprises of silicon oxide.

8. The method of manufacturing of claim 1 , wherein a thickness of the protective film is greater than or equal to about 1000Å and less than or equal to about 2000 Å.

9. The method of manufacturing of claim 1 , wherein the hard mask layer comprises silicon oxide and silicon oxynitride (SiON).

10. The method of manufacturing of claim 1 , wherein the method is applied when a step between the cell area and the logic area is at least about 500 nm.

11. The method of manufacturing of claim 1 , wherein the first conductive film is deposited before the protective film.

12. A method of manufacturing a non-volatile memory device, comprising:
forming a floating gate on a semiconductor substrate;
depositing a gate insulator, a first conductive film and a protective film on the floating gate;
patterning the protective film;
depositing a hard mask layer on the patterned protective film;
removing the hard mask layer and the patterned protective film to expose a surface of the first conductive film;
etching back the first conductive film; and
forming a control gate beside the floating gate.

13. The method of manufacturing of claim 12 , wherein the removing of the hard mask layer and the patterned protective film comprises:
forming a third mask pattern to expose the hard mask layer; and
wet etching the hard mask layer and the patterned protective film.

14. The method of manufacturing of claim 12 , wherein the control gate is higher than the logic gate.

15. The method of manufacturing of claim 12 , wherein the protective film comprises silicon oxide.

16. The method of manufacturing of claim 12 , wherein the hard mask layer comprises silicon oxide and silicon oxynitride (SiON).

17. The method of manufacturing of claim 12 , wherein the gate insulator is deposited before the first conductive film, and the first conductive film is deposited before the protective film.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Chang Yunseong
• Kang Yangbeom

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title