Semiconductor device including a silicon nitride dielectric layer and method for producing same

US10012883B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10012883-B2
Application numberUS-201515117524-A
CountryUS
Kind codeB2
Filing dateFeb 2, 2015
Priority dateFeb 10, 2014
Publication dateJul 3, 2018
Grant dateJul 3, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device ( 100 A) includes a substrate ( 11 ); a TFT ( 10 A) supported on the substrate, the TFT including an oxide semiconductor layer ( 16 ); an organic insulating layer ( 24 ) covering the TFT; a lower layer electrode ( 32 ) on the organic insulating layer; a dielectric layer ( 34 ) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode ( 36 ) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×10 21 atoms/cm 3 or less.

First claim

Opening claim text (preview).

The invention claimed is: 1. A production method of a semiconductor device comprising: step (a) of providing a substrate; step (b) of forming a thin film transistor on the substrate, the thin film transistor including an oxide semiconductor layer; step (c) of forming an organic insulating layer covering the thin film transistor; step (d) of forming a lower layer electrode on the organic insulating layer; step (e) of forming a dielectric layer on the lower layer electrode; and step (f) of forming an upper layer electrode on the dielectric layer, wherein step (e) is a step of forming a silicon nitride film as the dielectric layer, and is performed under film formation conditions such that the silicon nitride film has a hydrogen content of 5.33×10 21 atoms/cm 3 or less, and step (e) is performed by a plasma CVD technique, using a gaseous mixture containing SiH 4 and also containing NH 3 and/or N 2 , under film formation conditions defined by: an intra-chamber pressure of not less than 1200 mTorr and not more than 1500 mTorr; a substrate temperature of not less than 180° C. and not more than 220° C.; an inter-electrode distance of not less than 18 mm and not more than 25 mm; a ratio of the flow rate of SiH 4 to a total flow rate of the gaseous mixture being not less than 3% and not more than 5%; and a power density of 0.36 W/cm 2 or more. 2. The production method of a semiconductor device of claim 1 , wherein step (e) is performed with a power density of 0.49 W/cm 2 or less.

Assignees

Inventors

Classifications

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10012883B2 cover?
A semiconductor device ( 100 A) includes a substrate ( 11 ); a TFT ( 10 A) supported on the substrate, the TFT including an oxide semiconductor layer ( 16 ); an organic insulating layer ( 24 ) covering the TFT; a lower layer electrode ( 32 ) on the organic insulating layer; a dielectric layer ( 34 ) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper lay…
Who is the assignee on this patent?
Sharp Kk
What technology area does this patent fall under?
Primary CPC classification H10P14/69433. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 03 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).