TFT array substrate and method for producing the same

Patent metadata

Field	Value
Publication number	US-9640557-B2
Application number	US-201414222503-A
Country	US
Kind code	B2
Filing date	Mar 21, 2014
Priority date	Apr 3, 2013
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A TFT array substrate has an organic insulating film formed of a photosensitive organic resin material. A common electrode and a lead-out wiring are formed on the organic insulating film, and a pixel electrode is formed above the common electrode with an interlayer insulating film provided between them. The pixel electrode is connected to the lead-out wiring through a contact hole formed in the interlayer insulating film. The lead-out wiring and the common electrode are connected to a drain electrode and a common wiring, respectively, through contact holes formed in the organic insulating film. A metal cap film is provided on each of the lead-out wiring and the common electrode in the contact holes formed in the organic insulating film.

First claim

What is claimed is:

1. A TFT array substrate comprising:
a TFT element;
a common wiring supplied with a common potential;
an organic insulating film formed of a photosensitive organic resin material to cover a drain electrode of said TFT element and said common wiring;
a first contact hole formed in said organic insulating film, and reaching said drain electrode;
a second contact hole formed in said organic insulating film, and reaching said common wiring;
a first electrode and a lead-out wiring made of a transparent conductive film and extending on said organic insulating film;
an interlayer insulating film formed on said first electrode; and
a second electrode extending above said first electrode through said interlayer insulating film, and connected to said lead-out wiring through a third contact hole formed in said interlayer insulating film, wherein
one of said first electrode and said lead-out wiring is connected to said drain electrode through said first contact hole,
the other of said first electrode and said lead-out wiring is connected to said common wiring through said second contact hole,
a metal cap film is formed directly on each of said first electrode and said lead-out wiring in said first contact hole and said second contact hole on respective sides facing away from said drain electrode and said common wiring, and
said metal cap film is located so as to contact respective surfaces of said first electrode and said lead-out wiring all over a formation region of said metal cap film.

2. The TFT array substrate according to claim 1 , wherein
said metal cap film on said lead-out wiring is also formed on a bottom of said third contact hole.

3. The TFT array substrate according to claim 2 , wherein
said cap film on the bottom of said third contact hole has an opening smaller than an inner diameter of the bottom of said third contact hole.

Assignees

• Mitsubishi Electric Corp

Inventors

• Oda Koji
• Inoue Kazunori
• Ishiga Nobuaki
• Miyakawa Osamu

Classifications

• H01L27/124 Primary

  Electricity · mapped topic

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title