Apparatus and method for dynamically biased baseband current amplifier

Patent metadata

Field	Value
Publication number	US-10008984-B2
Application number	US-201715419668-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Sep 10, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

An amplifier circuit is provided. The amplifier circuit includes an amplifier stage; a plurality of variable transistors connected to the amplifier stage; a transconductor connected to at least one of the plurality of variable transistors; and a hybrid differential envelope detector and full-wave rectifier connected to the transconductor.

First claim

What is claimed is:

1. An amplifier circuit, comprising:
an amplifier stage;
a plurality of variable transistors connected to the amplifier stage;
a transconductor connected to at least one of the plurality of variable transistors; and
a hybrid differential envelope detector and full-wave rectifier connected to the transconductor.

2. The amplifier circuit of claim 1 , further comprising:
a variable resistor network connected to the amplifier stage;
an input interface connected to the variable resistor network and the hybrid differential envelope detector and full-wave rectifier; and
a controller connected to the variable resistor network, the hybrid differential envelope detector and full-wave rectifier, and the plurality of variable transistors.

3. The amplifier circuit of claim 1 , wherein the amplifier stage is implemented in a technology selected from complementary metal oxide semiconductor (CMOS), n-channel metal oxide semiconductor (NMOS), p-channel metal oxide semiconductor (PMOS), gallium arsenide (GaAs), indium GaAs, fin-shaped field effect transistor (FinFET), and bipolar.

4. The amplifier circuit of claim 2 , wherein the input interface is selected between a voltage input interface and a current input interface, wherein the current input interface comprises:
a differential amplifier, having a negative input for receiving a common mode voltage, a positive input, and an output;
a first n-channel field effect transistor (NFET), having a gate connected to the output of the differential amplifier, a source connected to a ground potential, and a drain;
a second NFET, having a gate connected to the output of the differential amplifier, a source connected to the ground potential, and a drain;
a current-output driving circuit, having a first output connected to the drain of the first NFET, and a second output connected to the drain of the second NFET; and
a compensation/averaging circuit connected between the drain of the first NFET and the drain of the second NFET.

5. The amplifier circuit of claim 1 , wherein each of the plurality of variable transistors is comprised of:
a plurality of switches, wherein each of the plurality of switches includes a first input connected to a ground potential, a second input connected to the first input of the variable transistor, a third input connected to the second input of the variable transistor, and an output; and
a plurality of n-channel field effect transistors (NFETs), wherein each NFET includes a source connected to the ground potential, a gate connected to the output of one of the plurality of switches, and a drain connected to the third input of the variable transistor.

6. The amplifier circuit of claim 2 , wherein the variable resistor network includes a first variable resistor between a first input and a positive output and a second variable resistor between a second input and a negative output.

7. The amplifier circuit of claim 2 , wherein the hybrid differential envelope detector and full-wave rectifier, comprises:
a first p-channel field effect transistor (PFET), having a source connected to a power supply voltage, a gate, and a drain connected to the gate;
a second PFET, having a source connected to the power supply voltage, a gate connected to the gate of the first PFET, and a drain;
a first n-channel field effect transistor (NFET), having a source, a gate for receiving a first input voltage, and a drain connected to the drain of the first PFET;
a second NFET, having a source connected to the source of the first NFET, a gate for receiving a second input voltage, and a drain connected to the drain of the first NFET;
a third NFET, having a source connected to the source of the first NFET, a gate at which a voltage V out appears, and a drain connected to the drain of the second PFET;
a fourth NFET, having a source connected to a ground potential, a gate for receiving a first bias voltage, and a drain connected to the source of the first NFET;
a fifth NFET, having a source connected to the gate of the third NFET, a gate connected to the drain of the second PFET, and a drain connected to the power supply voltage;
a variable transistor, having an input for receiving a second bias voltage, an input bus connected to the output bus of the controller, and a drain input connected to the gate of the third NFET; and
a variable capacitor, having an input bus connected to the output bus of the controller, and an output terminal connected to the gate of the third NFET, wherein the variable transistor comprises:
a first plurality of switches, wherein each of the first plurality of switches includes a first input connected to the ground potential, a second input for receiving the second bias voltage, a third input connected to the input bus, and an output; and
a first plurality of NFETs, wherein each NFET includes a source connected to the ground potential, a gate connected to the output of one of the first plurality of switches, and a drain connected to the drain input; and wherein the variable capacitor comprises:
a second plurality of switches, wherein each of the second plurality of switches includes a first input connected to the input bus, a second input, and an output connected to the output terminal; and
a second plurality of capacitors, wherein each capacitor has a first terminal connected to the ground potential, and a second terminal connected to the second input of one of the second plurality of switches.

8. The amplifier circuit of claim 1 , wherein the transconductor comprises:
a first p-channel field effect transistor (PFET), having a source connected to the power supply voltage, a gate, and a drain connected to the gate;
a second PFET, having a source connected to the power supply voltage, a gate, and a drain;
a third PFET, having a source connected to the power supply voltage, a gate connected to the gate of the second PFET, and a drain at which appears I dynamic ;
a first n-channel field effect transistor (NFET), having a source, a gate for receiving a reference voltage V BASE , and a drain connected to the drain of the first PFET;
a second NFET, having a source, a gate for receiving V out , and a drain connected to the drain of the second PFET;
a resistor, having a first terminal connected to the source of the first NFET, and a second terminal connected to the source of the second NFET;
a third NFET, having a source connected to a ground potential, a gate for receiving a third bias voltage, and a drain connected to the source of the first NFET; and
a fourth NFET, having a source connected to the ground potential, a gate for receiving the third bias voltage, and a drain connected to the source of the second NFET.

9. The amplifier circuit of claim 1 , wherein the amplifier stage is selected from a combination of a first differential amplifier and a second differential amplifier and a fully differential amplifier.

10. The amplifier circuit of claim 1 , further comprising a first filter between the amplifier stage and at least one the plurality of variable transistors and a second filter between the amplifier stage and at least another one of the plurality of variable transistors.

11. The amplifier circuit of claim 1 , further comprising:
a radio frequency (RF) upconverter connected to at least one of the plurality of variable transistors;
a power amplifier connected to the RF upconverter; and
an antenna connected to the power amplifier.

12. The amplifier circuit of claim 7 , wherein the transconductor comprises:
a first p-channel field effect transistor (PFET), having a source connected to the power supply voltage, a gate, and a drain connected to the gate;
a second PFET

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Seth Siddharth
• Son Sang Won
• Kwon Dae Hyun
• Venugopalan Sriramkumar
• Cho Thomas

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/381

  An active variable resistor, e.g. controlled transistor, being coupled in the output circuit of an amplifier to control the output · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F1/0233 Primary

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H04B2001/0416

  having gain or transmission power control · CPC title