Apparatus and method for dynamically biased baseband current amplifier

Patent metadata

Field	Value
Publication number	US-9559646-B2
Application number	US-201514819088-A
Country	US
Kind code	B2
Filing date	Aug 5, 2015
Priority date	Sep 10, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A dynamically biased baseband current amplifier is provided. The dynamically biased baseband current amplifier includes an input interface; a controller; a variable resistor network; an amplifier stage; a hybrid differential envelope detector and full-wave rectifier; a transconductor; a first variable transistor; a second variable transistor; a third variable transistor; and a fourth variable transistor.

First claim

What is claimed is:

1. A dynamically biased baseband current amplifier, comprising:
an input interface, having a positive output and a negative output;
a controller, having an output bus;
a variable resistor network, having a first input connected to the positive output of the input interface, having a second input connected to the negative output of the input interface, a control input connected to the output bus of the controller, having a positive output, and having a negative output;
an amplifier stage, having a first input for receiving a common mode voltage, having a second input connected to the positive output of the variable resistor network, having a third input connected to the negative output of the variable resistor network, having a first output, and having a second output;
a hybrid differential envelope detector and full-wave rectifier, having a first input connected to the output bus of the controller, having a second input connected to the positive output of the input interface, having a third input connected to the negative output of the input interface, and having an output;
a transconductor, having an input connected to the output of the hybrid differential envelope detector and full-wave rectifier, having a first output, and having a second output;
a first variable transistor, having a first input connected to the output bus of the controller, having a second input connected to the first output of the amplifier stage, and having a third input connected to the first output of the transconductor;
a second variable transistor, having a first input connected to the output bus of the controller, having a second input connected to the second output of the amplifier stage, and having a third input connected to the second output of the transconductor;
a third variable transistor, having a first input connected to the output bus of the controller, having a second input connected to the first output of the amplifier stage, and having a third input; and
a fourth variable transistor, having a first input connected to the output bus of the controller, having a second input connected to the second output of the amplifier stage, and having a third input.

2. The dynamically biased baseband current amplifier of claim 1 , wherein the dynamically biased baseband current amplifier is implemented in a technology selected from Complementary Metal Oxide Semiconductor (CMOS), N-channel Metal Oxide Semiconductor (NMOS), P-channel Metal Oxide Semiconductor (PMOS), Gallium Arsenide (GaAs), Indium GaAs, Fin-shaped Field Effect Transistor (FinFET), and Bipolar.

3. The dynamically biased baseband current amplifier of claim 1 , wherein the input interface is selected between a voltage input interface and a current input interface, wherein the current input interface comprises:
a differential amplifier, having a negative input for receiving a common mode voltage, having a positive input, and having an output;
a first N-channel Field Effect Transistor (NFET), having a gate connected to the output of the differential amplifier, having a source connected to a ground potential, and having a drain;
a second NFET, having a gate connected to the output of the differential amplifier, having a source connected to a ground potential, and having a drain;
a current-output driving circuit, having a first output connected to the drain of the first NFET, and having a second output connected to the drain of the second NFET; and
a compensation/averaging circuit connected between the drain of the first NFET and the drain of the second NFET.

4. The dynamically biased baseband current amplifier of claim 1 , wherein each of the first, second, third, and fourth variable transistor is comprised of:
a plurality of switches, wherein each of the plurality of switches includes a first input connected to a ground potential, a second input connected to the first input of the variable transistor, a third input connected to the second input of the variable transistor, and an output; and
a plurality of NFETs, wherein each NFET includes a source connected to the ground potential, a gate connected to the output of one of the plurality of switches, and a drain connected to the third input of the variable transistor.

5. The dynamically biased baseband current amplifier of claim 1 , wherein the variable resistor network is selected from one of a first variable resistor network, a second variable resistor network, and a third variable resistor,
wherein the first variable resistor network includes a first variable resistor between the first input and the positive output and a second variable resistor between the second input and the negative output,
wherein the second variable resistor network includes two variable resistors in series between the first input and the positive output and a variable capacitor between a connection between the two resistors and the ground potential, and another two variable resistors in series between the second input and the negative output and another variable capacitor between a connection between the two another resistors and the ground potential, and
wherein the third variable resistor network includes a first variable resistor between the first input and the positive output, a first variable capacitor between the first input and the ground potential, a second variable resistor between the second input and the negative output, a second variable capacitor between the second input and the ground potential, and a third variable resistor between the first input and the second input.

6. The dynamically biased baseband current amplifier of claim 1 , wherein the hybrid differential envelope detector and full-wave rectifier, comprises:
a first P-channel Field Effect Transistor (PFET), having a source connected to a power supply voltage, having a gate, and having a drain connected to the gate;
a second PFET, having a source connected to the power supply voltage, having a gate connected to the gate of the first PFET, and having a drain;
a first N-channel Field Effect Transistor (NFET), having a source, having a gate for receiving a first input voltage, and having a drain connected to the drain of the first PFET;
a second NFET, having a source connected to the source of the first NFET, having a gate for receiving a second input voltage, and having a drain connected to the drain of the first NFET;
a third NFET, having a source connected to the source of the first NFET, having a gate at which a voltage V out appears, and having a drain connected to the drain of the second PFET;
a fourth NFET, having a source connected to a ground potential, having a gate for receiving a first bias voltage, and having a drain connected to the source of the first NFET;
a fifth NFET, having a source connected to the gate of the third NFET, having a gate connected to the drain of the second PFET, and having a drain connected to the power supply voltage;
a variable transistor, having an input for receiving a second bias voltage, having an input bus connected to the output bus of the controller, and having a drain input connected to the gate of the third NFET; and
a variable capacitor, having an input bus connected to the output bus of the controller, and having an output terminal connected to the gate of the third NFET, wherein the variable transistor comprises:
a first plurality of switches, wherein each of the first plurality of switches includes a first input connected to the ground potential, a second input for receiving the second bias voltage, a third input connected to the input bus, and an output; and
a first plurality of NFETs, wherein each NFET includes a source connected to the ground potential, a gate connected to the output of one of the first plurality of switches, and a drain connected to the drain inp

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Seth Siddharth
• Son Sang Won
• Kwon Dae Hyun
• Venugopalan Sriramkumar
• Cho Thomas

Classifications

• H03F2200/546

  A tunable capacitance being present in an amplifier circuit · CPC title

• H03F2203/45112

  the biasing of the differential amplifier being controlled from the input or the output signal · CPC title

• H03F2200/91

  the amplifier has a current mode topology · CPC title

• H03F2200/381

  An active variable resistor, e.g. controlled transistor, being coupled in the output circuit of an amplifier to control the output · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title