Magnetoresistive random access memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10008539-B2
Application number	US-201615234257-A
Country	US
Kind code	B2
Filing date	Aug 11, 2016
Priority date	Dec 11, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A magnetoresistive random access memory (MRAM) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction; a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure.

First claim

What is claimed is:

1. A magnetoresistive random access memory (MRAM) device, comprising:
a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction;
a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction;
a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction;
a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and
a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure,
wherein the MTJ structures are arranged in a honey comb structure so that the MTJ structures are disposed at vertices and centers of hexagons, and
wherein the bit line structure includes a first portion extending in the first direction, and a second portion protruding from a sidewall of the first portion, the second portion electrically connecting two MTJ structures on neighboring two of the active patterns in the first direction, the MTJ structures being in the respective memory cells sharing the source line structure.

2. The device as claimed in claim 1 , wherein:
the active patterns include first and second active region rows disposed in the second direction, the first active region row including a plurality of first active patterns disposed in the first direction, and the second active region row including a plurality of second active patterns disposed in the first direction, and
two gate structures are disposed on each of the active patterns.

3. The device as claimed in claim 1 , further comprising:
a plurality of contact plugs contacting the drain regions of the active patterns, respectively; and
a pad pattern on each of the contact plugs, the pad pattern contacting a bottom of each of the MTJ structures.

4. The device as claimed in claim 1 , wherein the bit line structure includes:
a plurality of lower bit lines spaced apart from each other in the second direction, each of the lower bit lines electrically connecting two MTJ structures on neighboring two of the active patterns in the first direction, the MTJ structures being in the respective memory cells sharing the source line structure;
a bit line contact on each of the lower bit lines; and
an upper bit line on the bit line contact, the upper bit line extending in the first direction.

5. The device as claimed in claim 4 , wherein each of the lower bit lines extends in the second direction.

6. The device as claimed in claim 1 , wherein the bit line structure includes:
a plurality of lower bit lines spaced apart from each other in the second direction, each of the lower bit lines electrically connecting two MTJ structures on neighboring two of the active patterns in the first direction, the MTJ structures being in the respective memory cells sharing the source line structure; and
an upper bit line on each of the lower bit lines, the upper bit line extending in the first direction.

7. The device as claimed in claim 1 , further comprising contact plugs on the drain regions of the active patterns, respectively, wherein the MTJ structures contact the contact plugs, respectively.

8. The device as claimed in claim 7 , wherein:
the bit line structure connects the MTJ structures on the respective active patterns to each other, the active patterns sharing the source line structure, and
the bit line structure extends in the first direction.

9. The device as claimed in claim 8 , wherein a width in the second direction of the bit line structure is greater than a distance in the second direction between the drain regions of each of the active patterns.

10. A magnetoresistive random access memory (MRAM) device, comprising:
a substrate including an active pattern array thereon, the active pattern array including a plurality of active pattern rows disposed in a second direction, each of the active pattern rows including a plurality of active patterns disposed in a first direction substantially perpendicular to the second direction, and each of the active patterns extending in a diagonal direction with respect to the first direction;
a plurality of gate structures on the substrate, the gate structures extending in the second direction;
a source line structure electrically connected to source regions of the respective active patterns, the source line extending in the first direction;
a plurality of contact plugs contacting drain regions of the respective active patterns;
a plurality of pad patterns on the contact plugs, respectively;
a plurality of MTJ structures on the pad patterns, respectively, the MTJ structures being spaced apart from each other; and
a bit line structure electrically connecting the MTJ structures with each other, the MTJ structures being in memory cells sharing the source line structure,
wherein the MTJ structures are arranged in a honey comb structure so that the MTJ structures are disposed at vertices and centers of hexagons,
wherein the bit line structure includes a first portion extending in the first direction, and a second portion protruding from a sidewall of the first portion, the second portion electrically connecting two MTJ structures on neighboring two of the active patterns in the first direction.

11. The device as claimed in claim 10 , wherein first ones of the active patterns in respective odd-numbered active pattern rows and second ones of the active patterns in respective even-numbered active pattern rows are disposed with each other in a direction having an acute angle with respect to the second direction.

12. The device as claimed in claim 10 , wherein each of the pad patterns extends in the first direction to overlap a portion of an isolation layer between the active patterns, and the pad patterns are spaced apart from each other.

13. A magnetoresistive random access memory (MRAM) device, comprising:
a substrate including a plurality of active patterns spaced apart from one another along a first direction, each of the active patterns having a major axis that crosses the first direction and is inclined at an angle relative to the first direction;
a plurality of gate structures on the substrate, the gate structures extending in a second direction that is substantially perpendicular to the first direction;
a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction;
a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and
a bit line structure electrically connected to respective ones of the MTJ structures, the bit line structure being paired with the source line structure,
wherein the MTJ structures are arranged in a honey comb structure so that the MTJ structures are disposed at vertices and centers of hexagons, and
wherein the bit line structure includes a first portion extending in the first direction, and a second portion protruding from a sidewall of the first portion, the second portion electrically connecting two MTJ structures on neighboring two of the active patterns in the first direction, the MTJ structures being in respective memory cells sharing the source line structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Kyu
• Kim Sung-In
• Suh Ki-Seok

Classifications

• G11C11/1659

  Cell access · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• G11C11/1655 Primary

  Bit-line or column circuits · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title