Semiconductor package

Patent metadata

Field	Value
Publication number	US-10008533-B2
Application number	US-201615346929-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Dec 1, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A semiconductor package device includes a first semiconductor package including a first package substrate and a semiconductor chip stacked on the first package substrate, and a second semiconductor package stacked on the first semiconductor package. The second semiconductor package includes a second package substrate, an image sensor chip stacked on the second package substrate, and a transparent substrate disposed on the image sensor chip. The first semiconductor chip may include a semiconductor memory device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and/or an image sensor driver circuit and may transfer, process and/or store signals output from the image sensor chip.

First claim

What is claimed is:

1. A semiconductor package device comprising:
a first semiconductor package comprising a first package substrate having an upper surface and a lower surface, and a semiconductor chip disposed on the upper surface of the first package substrate;
a second semiconductor package stacked on the first semiconductor package, the second semiconductor package comprising a second package substrate having an upper surface and a lower surface that faces toward the first semiconductor package , an image sensor chip disposed on a region of the upper surface of the second package substrate, a transparent substrate disposed on the image sensor chip, a pattern of adhesive interposed between the image sensor chip and the transparent substrate, and a resin layer disposed on the second package substrate in contact with the upper surface of the second package substrate at a location laterally outwardly of the image sensor chip; and
wherein the semiconductor chip of the first semiconductor package has a first surface facing towards the first package substrate and a second surface facing towards the second semiconductor package,
the transparent substrate has a top surface, a bottom surface facing towards the image sensor chip, and a side surface extending from the bottom surface to the top surface,
the pattern of adhesive has a bottom surface in contact with the image sensor chip, and a top surface in contact with the bottom surface of the transparent substrate, and
the resin layer has a side surface extending from the transparent substrate to the upper surface of the second package substrate at location laterally of the image sensor chip, and extends around the image sensor chip, pattern of adhesive and at least a lower part of the transparent substrate.

2. The semiconductor package device of claim 1 , wherein a distance between a top surface of the second package substrate and the side surface of the resin layer gradually decreases as a horizontal distance from the transparent substrate increases.

3. The semiconductor package device of claim 1 , wherein the side surface of the resin layer is inclined with respect to a vertical direction.

4. The semiconductor package device of claim 1 , wherein a width of the image sensor chip is greater than that of the transparent substrate.

5. The semiconductor package device of claim 1 , wherein the pattern of adhesive extends in a ring alongside an outer peripheral edge of the transparent substrate, and
the pattern of adhesive delimits a space between the image sensor chip and the transparent substrate, and air occupies the space.

6. The semiconductor package device of claim 1 , wherein the pattern of adhesive extends in a ring alongside an outer peripheral edge of the transparent substrate, and
further comprising a transparent epoxy layer occupying a space delimited by the adhesive pattern between the image sensor chip and the transparent substrate.

7. The semiconductor package device of claim 1 , wherein a top surface and at least an upper part of the side surface of the transparent substrate are not covered by the resin layer.

8. The semiconductor package device of claim 1 , wherein the top surface of the transparent substrate is not covered by the resin layer, and the resin layer covers the entire side surface of the transparent substrate from the bottom surface to the top surface of the transparent substrate.

9. The semiconductor package device of claim 1 , wherein the first semiconductor package further comprises: solder balls interposed between the first package substrate and the semiconductor chip, and
the second semiconductor package further comprises: bonding wires electrically connecting the image sensor chip to the second package substrate,
the semiconductor package device further comprising:
connection terminals extending between the first semiconductor package and the second semiconductor package and electrically connecting the first and second semiconductor packages to each other.

10. The semiconductor package device of claim 1 , wherein a width of the top surface of the adhesive pattern is greater than a width of the bottom surface of the adhesive pattern.

11. The semiconductor package device of claim 1 , wherein the resin layer also contacts at least part of the side surface of the transparent substrate.

12. The semiconductor package device of claim 1 , wherein the second semiconductor package further comprises: a molding layer disposed on the resin layer and extending around the transparent substrate, and
wherein a top surface of the molding layer is coplanar with a top surface of the transparent substrate.

13. The semiconductor package device of claim 12 , wherein the elastic modulus of the resin layer is greater than that of the molding layer.

14. A semiconductor package device comprising:
a first semiconductor package comprising a first package substrate and a semiconductor chip stacked on the first package substrate; and
a second semiconductor package stacked on the first semiconductor package, the second semiconductor package comprising a second package substrate, an image sensor chip stacked on the second package substrate, a transparent substrate disposed on the image sensor chip, a pattern of adhesive interposed between the image sensor chip and the transparent substrate, a resin layer disposed on the second package substrate and extending around the transparent substrate, and a molding layer disposed on the resin layer and extending around the transparent substrate,
wherein the pattern of adhesive has a bottom surface in contact with the image sensor chip, and a top surface in contact with the bottom surface of the transparent substrate, and
a top surface of the molding layer is coplanar with a top surface of the transparent substrate.

15. The semiconductor package device of claim 14 , wherein the elastic modulus of the resin layer is greater than that of the molding layer.

16. A semiconductor package device comprising:
a first semiconductor package comprising a first printed circuit board (PCB) having a top surface and a bottom surface, a first semiconductor chip disposed on and flip-chip bonded to the top surface of the first PCB such that an active surface of the semiconductor chip faces the top surface of the first PCB, and connection terminals disposed laterally of the first semiconductor chip and electrically connected to the first PCB at the top surface of the first PCB; and
a second semiconductor package stacked on and physically connected to the first semiconductor package, the second semiconductor package comprising a second printed circuit board (PCB) having a top surface and a bottom surface that faces the first semiconductor package and at which the second PCB is electrically connected to the connection terminals of the first semiconductor package, an image sensor chip disposed on the second PCB and electrically connected to the second PCB, and a transparent substrate disposed over the image sensor chip as spaced vertically therefrom,
wherein the first semiconductor chip comprises at least one semiconductor device selected from the group consisting of a semiconductor memory device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and an image sensor driver circuit, and
the first semiconductor chip is electrically connected to the image sensor chip via the first PCB, the connection terminals and the second PCB, whereby the first semiconductor chip transfers, processes and/or stores signals output from the image sensor chip.

17. The semiconductor packag

Assignees

• Jun Hyunsu
• Samsung Electronics Co Ltd

Inventors

• Jun Hyunsu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/0198

  batch processes · CPC title