Oxidation resistant barrier metal process for semiconductor devices

Patent metadata

Field	Value
Publication number	US-10008450-B2
Application number	US-201715615963-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Dec 18, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an underlying metal geometry;
a dielectric layer on the underlying metal geometry;
a contact opening through the dielectric layer wherein the contact opening stops on the underlying metal geometry;
an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening;
an oxidation resistant barrier layer wherein the oxidation resistant barrier layer is disposed between the underlying metal geometry and overlying metal geometry and wherein the oxidation resistant barrier layer is formed of tantalum-nitride (TaN) or titanium-nitride (TiN) with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm; and
an interdiffusion barrier layer disposed between the underlying metal geometry and the oxidation resistant barrier layer, wherein the interdiffusion barrier layer is TaN or TiN with a thickness between 60 nm and 90 nm and a nitrogen content between 0 and 12 atomic percent.

2. The integrated circuit of claim 1 , wherein the oxidation resistant barrier layer extends under the contact opening.

3. The integrated circuit of claim 1 , wherein the oxidation resistant barrier layer extends along sides and bottom of the contact opening.

4. The integrated circuit of claim 1 , wherein the oxidation resistant barrier layer is formed of TaN with a thickness between 5 and 15 nm and with a nitrogen content between 20 and 35 atomic percent.

5. The integrated circuit of claim 1 , wherein the oxidation resistant barrier layer is formed of TaN with a thickness of about 10 nm and a nitrogen content of about 28 atomic percent.

6. An integrated circuit, comprising:
a first metal geometry;
a dielectric layer on the first metal geometry;
a contact opening through the dielectric layer over the first metal geometry;
a second metal geometry wherein a portion of the second metal geometry fills a portion of the contact opening; and
an oxidation resistant barrier layer wherein the oxidation resistant barrier layer is disposed between the first metal geometry and the second metal geometry and wherein the oxidation resistant barrier layer is formed of tantalum-nitride (TaN) or titanium-nitride (TiN) with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm, wherein the oxidation resistant barrier layer extends under the contact opening.

7. The integrated circuit of claim 6 , wherein a portion of the oxidation resistant barrier layer extends between the dielectric layer and the first metal geometry.

8. The integrated circuit of claim 6 , further comprising an interdiffusion barrier layer disposed between the first metal geometry and the oxidation resistant barrier layer.

9. The integrated circuit of claim 8 , wherein the interdiffusion barrier layer is TaN or TiN with a thickness between 60 nm and 90 nm and a nitrogen content between 0 and 12 atomic percent.

10. The integrated circuit of claim 6 , wherein the oxidation resistant barrier layer is formed of TaN with a thickness between 5 and 15 nm and with a nitrogen content between 20 and 35 atomic percent.

11. The integrated circuit of claim 6 , wherein the oxidation resistant barrier layer is formed of TaN with a thickness of about 10 nm and a nitrogen content of about 28 atomic percent.

12. An integrated circuit, comprising:
a first metal geometry;
a dielectric layer on the first metal geometry;
a contact opening through the dielectric layer over the first metal geometry;
a second metal geometry wherein a portion of the second metal geometry fills a portion of the contact opening;
an oxidation resistant barrier layer wherein the oxidation resistant barrier layer is disposed between the first metal geometry and the second metal geometry and wherein the oxidation resistant barrier layer is formed of tantalum-nitride (TaN) or titanium-nitride (TiN) with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm; and
an interdiffusion barrier layer disposed between the first metal geometry and the oxidation resistant barrier layer, wherein the interdiffusion barrier layer is TaN or TiN with a thickness between 60 nm and 90 nm and a nitrogen content between 0 and 12 atomic percent.

13. The integrated circuit of claim 12 , wherein a portion of the oxidation resistant barrier layer is between the dielectric layer and the first metal geometry.

14. The integrated circuit of claim 12 , wherein the oxidation resistant barrier layer extends along sides and bottom of the contact opening.

15. The integrated circuit of claim 12 , wherein the oxidation resistant barrier layer is formed of TaN with a thickness between 5 and 15 nm and with a nitrogen content between 20 and 35 atomic percent.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey A
• Udayakumar Kezhakkedath R
• Warninghoff Eric H
• Merriam Alan G
• Faust Rick A

Classifications

• H10W72/019

  of bond pads · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title