Block health monitoring using threshold voltage of dummy memory cells

Patent metadata

Field	Value
Publication number	US-10008277-B2
Application number	US-201615262262-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Sep 12, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.

First claim

We claim:

1. An apparatus, comprising:
one set of memory cells in a block, the one set of memory cells comprising data memory cells and dummy memory cells arranged in NAND strings, each NAND string comprising one of the data memory cells adjacent to one of the dummy memory cell; and
a control circuit, the control circuit is configured to:
program threshold voltages of the dummy memory cells to a voltage above a verify level, wherein the threshold voltages of the dummy memory cells are exceeded by threshold voltages of a highest programmed data state of the data memory cells;
perform an evaluation of the threshold voltages of the dummy memory cells, the evaluation determines a number of the dummy memory cells for which the threshold voltages have downshifted below a demarcation voltage; and
based on the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage, perform a corrective action for the data memory cells, wherein the control circuit, to perform the corrective action, is configured to lower a read voltage for the highest programmed data state in a read operation involving the data memory cells when the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage exceeds a first number N 1 but not a second number N 2 >N 1 , and to recover data from the data memory cells when the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage exceeds the second number N 2 .

2. The apparatus of claim 1 , wherein:
the one set of memory cells is in one sub-block of a block;
another set of memory cells comprising data memory cells and dummy memory cells is in another sub-block of the block; and
the control circuit is configured to perform the evaluation separate from an evaluation of threshold voltages of the dummy memory cells in the another sub-block, and based on the evaluation of the threshold voltages of the dummy memory cells in the another sub-block, to perform the corrective action for the data memory cells of the another set of memory cells, separately from the performing the corrective action for the data memory cells of the one set of memory cells.

3. The apparatus of claim 2 , wherein:
the one set of memory cells are in NAND strings in the one sub-block; and
the another set of memory cells are in NAND strings in the another sub-block.

4. The apparatus of claim 1 , wherein:
the evaluation compares the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage to a specified number; and
the circuit is configured to determine the specified number as a function of a number of program-erase cycles in the block.

5. The apparatus of claim 1 , wherein:
the read operation involves selected data memory cells of the one set of memory cells; and
to perform the corrective action, the control circuit is configured to lower the read voltage based on a position of the selected data memory cells in the NAND strings such that the read voltage is lower when the selected data memory cells are at an edge of the NAND strings than when the selected data memory cells are not at an edge of the NAND strings.

6. The apparatus of claim 1 , wherein:
the control circuit, to perform the corrective action, is configured to use a lower initial program voltage in a next programming operation for the one set of memory cells compared to an initial program voltage used in a past programming operation for the one set of memory cells.

7. The apparatus of claim 1 , wherein:
the control circuit, to perform the corrective action, is configured to use a higher initial erase voltage in a next erase operation for the one set of memory cells compared to an initial erase voltage used in a past erasing operation for the one set of memory cells.

8. The apparatus of claim 1 , wherein:
the control circuit is configured to perform a plurality of program-erase cycles for the data memory cells; and
the evaluation determines an amount by which the threshold voltages of the dummy memory cells have downshifted below the demarcation voltage after the plurality of program-erase cycles.

9. The apparatus of claim 1 , wherein:
the control circuit is configured to trigger the evaluation of the dummy memory cells in response to a determination that a number of program-erase cycles in the block has reached a threshold.

10. The apparatus of claim 1 , wherein:
the control circuit is configured to trigger the evaluation of the dummy memory cells in response to a command to perform a read operation involving selected data memory cells of the one set of memory cells, and to perform the corrective action during the read operation.

11. The apparatus of claim 1 , wherein:
the control circuit is configured to erase the dummy memory cells less deeply than the data memory cells in an erase operation.

12. The apparatus of claim 1 , wherein:
the data memory cells are programmed to a plurality of programmed data states including a top half of the programmed states and a bottom half of the programmed states; and
the threshold voltages of the dummy memory cells are among lower states in the bottom half of the programmed states.

13. The apparatus of claim 1 , wherein:
the control circuit is configured to set a flag in a register indicating the block is bad when the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage exceeds a specified number.

14. The apparatus of claim 1 , wherein:
to perform the corrective action, the control circuit is configured to mark the data memory cells as having a reduced endurance when the number of the dummy memory cells for which the threshold voltages have downshifted below the demarcation voltage exceeds the first number N 1 but not the second number N 2 .

15. A method, comprising:
programming threshold voltages of dummy memory cells in a set of memory cells to a voltage above a verify level, wherein the dummy memory cells are adjacent to data memory cells in NAND strings;
determining a degree to which the threshold voltages have downshifted after a specified number of program-erase cycles of the data memory cells in which threshold voltages of the dummy memory cells are exceeded by threshold voltages of a highest programmed data state of the data memory cells by determining a number of the dummy memory cells having a threshold voltage below a demarcation voltage; and
performing a corrective action for the data memory cells based on the number of dummy memory cells having the threshold voltage below the demarcation voltage, wherein the performing the corrective action comprises lowering a read voltage for a highest programmed data state in a read operation involving the data memory cells when the number of the dummy memory cells having the threshold voltage below the demarcation voltage exceeds a first number but not a second number, and recovering data from the data memory cells when the number of the dummy memory cells having the threshold voltage below the demarcation voltage exceeds the second number.

16. The method of claim 15 , wherein:
the lowering the read voltage comprises lowering the read voltage by a first adjustment amount when the number of dummy memory cells having the threshold voltage below the demarcation voltage is between the first number and another number which is higher than the first number and lower than the second number and by a second adjustment amount when the number of dummy memory cells havin

Assignees

• Sandisk Technologies Llc

Inventors

• Pang Liang
• Yu Xuehong
• Dong Yingda
• Yang Nian Niles

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title