Memory block cycling based on memory wear or data retention

Patent metadata

Field	Value
Publication number	US-2016180959-A1
Application number	US-201514977155-A
Country	US
Kind code	A1
Filing date	Dec 21, 2015
Priority date	Dec 22, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

First claim

We claim:

1 . A system for cycling memory blocks comprising:
a measurement module configured to measure voltages of memory cells in the memory blocks; a generation module configured to periodically generate a voltage distribution based on the measured voltages of the memory cells; a comparison module configured to compare the generated voltage distributions; and an analysis module configured to calculate a wear for each of the memory blocks based on the comparison and further configured to cycle the memory blocks based on the calculated wear for each of the memory blocks.

2 . The memory system of claim 1 wherein the calculation of the wear is based on a change in shape of the voltage distribution.

3 . The memory system of claim 2 wherein the change in shape comprises changes in a standard deviation of the shape or comprises changes in a skewness of the shape.

4 . The memory system of claim 1 wherein the calculation of the wear is based on an analysis of bit error rate (BER).

5 . The memory system of claim 1 wherein the cycling of the memory blocks comprises:
utilizing the memory blocks with a lowest calculated wear; and
avoiding the memory blocks with a highest calculated wear.

6 . The memory system of claim 5 wherein the cycling evens out the calculated wear across the memory blocks and an overall endurance is improved by avoiding the memory blocks with the highest calculated wear.

7 . A method for improving memory system endurance, the method comprising:
calculating a wear for each memory block in the memory system; and cycling usage based on the calculated wear for each of the memory blocks, wherein the memory blocks with a higher calculated wear are avoided.

8 . The method of claim 7 wherein the calculating a wear comprises:
periodically determining a cell voltage distribution of cells in the memory blocks;
measuring changes in the cell voltage distribution from the periodic determinations; and
calculating changes in a shape of the cell voltage distribution, wherein the calculated changes in the shape indicate the wear.

9 . The method of claim 8 wherein the changes in the shape comprises changes in a standard deviation of the shape of the cell voltage distribution or changes in a skewness of the shape of the cell voltage distribution.

10 . The method of claim 7 wherein the cycling of the memory blocks further comprises increasing utilization of the memory blocks with a lowest calculated wear.

11 . A system for improving data retention of memory blocks comprising:
a measurement module configured to measure voltages of memory cells in the memory blocks; a generation module configured to periodically generate a voltage distribution based on the measured voltages of the memory cells; a comparison module configured to compare the generated voltage distributions; and an analysis module configured to calculate a data retention value for each of the memory blocks based on the comparison and further configured to cycle the memory blocks based on the calculated data retention values.

12 . The memory system of claim 11 wherein the calculation of the data retention values is based on a change in location of the voltage distribution.

13 . The memory system of claim 12 wherein the change in location comprises a calculation of a change in at least one of a mean, a mode, or a median of the voltage distribution.

14 . The memory system of claim 11 wherein the cycling of the memory blocks comprises:
utilizing the memory blocks with a lowest calculated data retention value for short term storage; and
utilizing the memory blocks with a highest calculated data retention value for long term storage.

15 . The memory system of claim 14 wherein the memory blocks with the lowest calculated data retention value are selected for reclamation and the cycling normalizes data retention values across the blocks.

16 . The memory system of claim 11 wherein the calculation of the data retention values is based on an analysis of bit error rate (BER).

17 . A method for data retention in a memory device, the method comprising:
performing the following on blocks in a memory device with a controller:
calculating a data retention rate for each of the blocks; and
reducing usage of the blocks with a higher calculated data retention rate.

18 . The method of claim 17 wherein the calculating the data retention rate for each of the blocks comprises:
periodically determining a cell voltage distribution of cells in the blocks;
measuring changes in the cell voltage distribution from the periodic determinations; and
calculating changes in a shape of the cell voltage distribution, wherein the calculated changes comprises a change in a location of the shape that indicate the data retention rate.

19 . The method of claim 18 wherein the change in location comprises a calculation of a change in at least one of a mean, a mode, or a median of the voltage distribution.

20 . The method of claim 17 wherein the blocks with a lower calculated data retention value are selected for reclamation.

Assignees

• Sandisk Technologies Inc

Inventors

• Darragh Neil Richard
• Gorobets Sergey Anatolievich
• Parker Liam Michael

Classifications

• G06F11/008

  Reliability or availability analysis · CPC title

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title