Gate driver on array circuit and display device capable of prolonging charging time of pixel

Patent metadata

Field	Value
Publication number	US-10008170-B2
Application number	US-201514905879-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Nov 24, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

The present invention proposes a GOA circuit and a display device adopting the same. The GOA circuit includes thirteen transistors and a first capacitor. The GOA circuit can be driven in 2D and 3D driving modes to prolong charging time of each pixel. Each two GOA circuit units share a set of Nth stage start pulse signals, Nth stage gate pulse signals and eight clock pulse signals. Because the charging time of each pixel is prolonged, the display device can show images with better display quality.

First claim

What is claimed is:

1. A gate driver on array (GOA) circuit, comprising a plurality of GOA units, connected in cascade, with an Nth stage GOA unit outputting a Nth stage gate pulse signal from an output terminal; the Nth stage GOA unit comprises:
a first switch component, comprising a first control terminal, a first connecting terminal and a second connecting terminal, with the first connecting terminal and the first control terminal connected to a (N−4)th stage start pulse signal or a (N−4)th stage gate pulse signal;
a second switch component, comprising a second control terminal, a third connecting terminal and a fourth connecting terminal, with the second control terminal connected to the Nth pre-charged voltage node, the third connecting terminal connected to the first clock signal, and the fourth connecting terminal connected to the output terminal;
a third switch component, comprising a third control terminal, a fifth connecting terminal and a sixth connecting terminal, with the third control terminal connected to the second connecting terminal, the fifth connecting terminal connected to the first clock signal, and the sixth connecting terminal connected to the Nth stage start pulse signal;
a fourth switch component, comprising a fourth control terminal, a seventh connecting terminal and an eighth connecting terminal, with the fourth control terminal and the seventh connecting terminal connected to the first clock signal;
a fifth switch component, comprising a fifth control terminal, a ninth connecting terminal and a tenth connecting terminal, with the fifth control terminal receiving the Nth stage pre-charged voltage node, the ninth connecting terminal connected to the eighth connecting terminal, and the tenth connecting terminal connected to a first voltage source;
a sixth switch component, comprising a sixth control terminal, an eleventh connecting terminal and a twelfth connecting terminal, with the sixth control terminal connected to the eighth connecting terminal, the eleventh connecting terminal connected to the first clock signal, and the twelfth connecting terminal connected to the first voltage source;
a seventh switch component, comprising a seventh control terminal, a thirteenth connecting terminal and a fourteenth connecting terminal, with the seventh control terminal connected to the fifth control terminal, the thirteenth connecting terminal connected to the twelfth connecting terminal, and the fourteenth connecting terminal connected to the first voltage source;
an eighth switch component, comprising an eighth control terminal, a fifteenth connecting terminal and a sixteenth connecting terminal, with the eighth control terminal connected to the twelfth connecting terminal and the thirteenth connecting terminal, the fifteenth connecting terminal connected to the third control terminal, and the sixteenth connecting terminal connected to the output terminal;
a ninth switch component, comprising a ninth control terminal, a seventeenth connecting terminal and an eighteenth connecting terminal, with the ninth control terminal connected to the eighth control terminal, the seventeenth control terminal connected to the output terminal, and the eighteenth connecting terminal connected to the first voltage source;
a tenth switch component, comprising a tenth control terminal, a nineteenth connecting terminal and a twentieth connecting terminal, with the tenth control terminal connected to a second clock signal, the nineteenth connecting terminal connected to the output terminal, and the twentieth connecting terminal receiving the (N−4)th stage start pulse signal or gate pulse signal;
an eleventh switch component, comprising an eleventh control terminal, a twenty-first connecting terminal and a twenty-second connecting terminal, with the eleventh control terminal connected to the second clock signal, the twenty-first connecting terminal connected to the output terminal, and the twenty-second connecting terminal connected to the first voltage source;
a twelfth switch component, comprising a twelfth control terminal, a twenty-third connecting terminal and a twenty-fourth connecting terminal, with the twelfth control terminal connected to a (N+4)th stage start pulse signal or gate pulse signal, the twenty-third pathway connected to the third control terminal, and the twenty-fourth connecting terminal connected to the first voltage source; and
a thirteenth switch component, comprising a thirteenth control terminal, a twenty-fifth connecting terminal and a twenty-sixth connecting terminal, with the thirteenth control terminal receiving the (N+4)th stage start pulse signal or gate pulse signal, the twenty-fifth connecting terminal connected to the output terminal, and the twenty-sixth connecting terminal connected to the first voltage source,
where N is an integer greater than 4.

2. The GOA circuit of claim 1 , further comprising a capacitor, with its two ends connected to the third control terminal and the output terminal respectively.

3. The GOA circuit of claim 1 , wherein all switch components, from the first to the thirteenth, are N-type metal oxide semiconductor (NMOS) transistors.

4. The GOA circuit of claim 1 , wherein all switch components, from the first to the thirteenth, are P-type metal oxide semiconductor (PMOS) transistors.

5. The GOA circuit of claim 1 , wherein the first clock signal and the second clock pulse signal are inversed.

6. The GOA circuit of claim 1 , wherein a duty ratio of the first clock signal and the second clock pulse signal is 50%.

7. The GOA circuit of claim 1 , wherein the pulse width of the first clock signal of the GOA circuit when driving two-dimensional (2D) images is twice the pulse width of the first clock signal of the GOA circuit when driving three-dimensional (3D) images.

8. The GOA circuit of claim 1 , wherein the pulse width of the first clock signal of the GOA circuit when driving 2D images are twice the pulse width of the first clock signal of the GOA circuit when driving 3D images.

9. The GOA circuit of claim 8 , wherein the phase difference between the first clock signal connected to the Nth stage GOA circuit unit and the first clock signal connected to the (N+1)th stage GOA circuit unit is one-fourth of the pulse width of the first clock signal when the GOA circuit is driving 2D images.

10. The GOA circuit of claim 8 , wherein no phase difference exists between the first clock signal connected to the Nth stage GOA circuit unit and the first clock signal connected to the (N+1)th stage GOA circuit unit, and no phase difference exists between the first clock signal connected to the (N+2)th stage GOA circuit unit and the first clock signal connected to the (N+3)th stage GOA circuit unit when the GOA circuit is driving 3D images.

11. The GOA circuit of claim 10 , wherein the phase difference between the first clock signal connected to the Nth stage GOA unit and the first clock signal connected to the (N+2)th stage GOA unit is half of the pulse width of the first clock signal.

12. A display device, comprising:
a liquid crystal display panel for showing images;
a gate driver on array (GOA) circuit, integrated on the liquid crystal display panel, the GOA circuit comprising a plurality of GOA units connected in cascade, with an Nth stage GOA unit outputting a Nth stage gate pulse signal from an output terminal; the Nth stage GOA unit comprises:
a first switch component, comprising a first control terminal, a first connecting terminal and a second connecting terminal, with the first connecting terminal and the first control terminal connected to a (N−4)th stage start pulse signal or a (N−4)th stage gate pulse signal;
a second sw

Assignees

• Shenzhen China Star Optoelect

Inventors

• Wang Xiaoxiao
• Du Peng

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title