Computing platform interface with memory management

Patent metadata

Field	Value
Publication number	US-10007528-B2
Application number	US-201213683748-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 22, 2011
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

First claim

What is claimed is:

1. An apparatus for memory power management to save power, the apparatus comprising:
one or more memories; and
a firmware including Advanced Configuration and Power Interface (ACPI) components to build, at the time of boot, a memory power state table (MPST) structure, wherein the MPST structure is associated with the one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,
wherein the MPST table structure is stored in a dedicated firmware memory space,
wherein firmware is to use the information in the MPST table to allow the apparatus to save power,
wherein data in the MPST structure is updated by a platform, and
wherein the firmware to update some parts of the MPST structure while the platform is operating.

2. The apparatus of claim 1 , wherein the MPST structure includes a table with power state values.

3. The apparatus of claim 1 , wherein the MPST structure includes a table with memory power node structure definitions for the one or more memories.

4. The apparatus of claim 1 , wherein the MPST structure includes a table with memory power state structure definitions.

5. The apparatus of claim 1 , wherein the MPST structure includes a common memory aggregator device structure.

6. The apparatus of claim 1 , wherein the one or more memories and the firmware are part of a computer platform that is one of a:
smart-phone,
tablet, or
server computer.

7. The apparatus of claim 1 , wherein the memory power nodes represent logical memory regions, associated with the one or more memories, that can be transitioned in and out of memory power states.

8. The apparatus of claim 1 , wherein each of the memory power nodes is uniquely identified.

9. The apparatus of claim 1 , wherein the memory power state characteristics describe memory power state transitions.

10. The apparatus of claim 1 , wherein the firmware to create the MPST structure in a dedicated firmware memory space.

11. A method for memory power management to save power, the method comprising:
building, at the time of boot, a memory power state table (MPST) structure compatible with an Advanced Configuration and Power Interface (ACPI), wherein the MPST structure is associated with one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,
wherein the MPST table structure is stored in a dedicated firmware memory space,
wherein the information in the MPST table is used to allow an apparatus to save power,
wherein data in the MPST structure is updated by a platform, and
wherein the firmware is to update some parts of the MPST structure while the platform is operating.

12. The method of claim 11 , wherein the MPST structure includes a table with power state values.

13. The method of claim 11 , wherein the MPST structure includes a table with memory power node structure definitions for the one or more memories.

14. The method of claim 11 , wherein the MPST structure includes a table with memory power state structure definitions.

15. The method of claim 11 , wherein the MPST structure includes a common memory aggregator device structure.

16. The method of claim 11 , wherein the memory power nodes represent logical memory regions, associated with the one or more memories, that can be transitioned in and out of memory power states.

17. The method of claim 11 , wherein each of the memory power nodes is uniquely identified.

18. The method of claim 11 , wherein the memory power state characteristics describe memory power state transitions.

19. A non-transitory computer executable storage media having instructions stored thereon that when executed cause a one or more processors to perform one or more operation for memory power management to save power, the method comprising:
building, at the time of boot, a memory power state table (MPST) structure compatible with an Advanced Configuration and Power Interface (ACPI), wherein the MPST structure is associated with one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,
wherein the MPST table structure is stored in a dedicated firmware memory space,
wherein the information in the MPST table is used to allow an apparatus to save power,
wherein data in the MPST structure is updated by a platform, and
wherein the firmware is to update some parts of the MPST structure while the platform is operating.

Assignees

• Intel Corp

Inventors

• Therien Guy M
• Diefenbaugh Paul
• Aggarwal Anil
• Henroid Andrew D
• Shrall Jeremy J
• Rotem Efraim
• Sistla Krishnakanth V
• Weissmann Eliezer
• Kumar Mohan
• Jayakumar Sarathy
• Vargas Jose Andy
• Chandwani Neelam
• Rothman Michael A
• Gough Robert
• Doran Mark

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F9/384

  Register renaming · CPC title