Fin-based semiconductor devices and methods

Patent metadata

Field	Value
Publication number	US-10002954-B2
Application number	US-201415100286-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2014
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin located on a substrate, the first fin comprising a first material, a second material, a third material, and a fourth material, wherein the first fin has a first portion and a second portion, wherein the first portion includes the first material, the second material, the third material, and the fourth material, wherein the second portion includes the first material and the second material, wherein the first material of the second portion is materially contiguous with the first material of the first portion, wherein the second material of the second portion is materially contiguous with the second material of the first portion, and wherein:
the first material is located between the second material and the substrate,
the second material is located between the third material and the first material,
the third material is located between the fourth material and the second material,
the first material and the third material include a first type of extrinsic semiconductor, and
the second material and the fourth material include a second type of extrinsic semiconductor, the second type different from the first type; and

a second fin located on the substrate, laterally separated from the first fin, wherein the second fin has a material that is materially contiguous with at least one of the first material, the second material, the third material, or the fourth material;
a first conductive contact located on the fourth material; and
a second conductive contact located on the second material of the second portion.

2. The semiconductor device of claim 1 , wherein the first type of extrinsic semiconductor is one of an N-type and a P-type, and wherein the second type of extrinsic semiconductor is an N-type if the first type of extrinsic semiconductor is a P-type, or a P-type if the first type of extrinsic semiconductor is an N-type.

3. The semiconductor device of claim 1 , wherein the first conductive contact is located on a first surface of the fourth material of the first portion, the second conductive contact is located on a second surface of the second material of the second portion, and the first surface and the second surface are substantially in a same plane.

4. The semiconductor device of claim 1 , wherein the fourth material of the first portion and the second material of the second portion are laterally separated by a material that is materially contiguous with the third material of the first portion.

5. The semiconductor device of claim 1 , further comprising a third conductive contact located on the second fin.

6. The semiconductor device of claim 1 , wherein the second fin is laterally separated from the first fin by an insulator.

7. The semiconductor device of claim 1 , wherein the semiconductor device is a thyristor.

8. The semiconductor device of claim 1 , wherein the material of the second fin is materially contiguous with the first material.

9. A method of fabricating a semiconductor device, comprising:
forming first and second fins on a substrate, the first and second fins extending away from the substrate and laterally separated; and
forming first, second, third and fourth dopant source films of first, second, third and fourth dopants, respectively, in contact with a side surface of a portion of the first fin, wherein:
the first dopant source film is located in contact with a side surface of a portion of the first fin, in contact with the second fin, and between the second dopant source film and the substrate,
the second dopant source film is located in contact with the side surface of the portion of the first fin and between the third dopant source film and the first dopant source film,
the third dopant source film is located in contact with the side surface of the portion of the first fin and between the fourth dopant source film and the second dopant source film,
the first and third dopant source films include a dopant for a first type of extrinsic semiconductor, and
the second and fourth dopant source films include a dopant for a second type of extrinsic semiconductor, the second type different from the first type.

10. The method of claim 9 , wherein the fourth dopant source film is in contact with a top surface of the portion of the first fin.

11. The method of claim 9 , further comprising:
driving dopants from the first, second, third and fourth dopant source films into the portion of the first fin to form first, second, third and fourth materials, wherein:
the first material is located between the second material and the substrate,
the second material is located between the third material and the first material,
the third material is located between the fourth material and the second material,
the first and third materials are formed from the first type of extrinsic semiconductor, and
the second and fourth materials are formed from the second type of extrinsic semiconductor.

12. The method of claim 11 , further comprising:
forming a first conductive contact on the fourth material; and
forming a second conductive contact on a material that is materially contiguous with the second material.

13. The method of claim 12 , further comprising:
forming a third conductive contact on a material of the second fin that is materially contiguous with the first material.

14. The method of claim 12 , wherein the first, second, third and fourth materials are included in a thyristor.

15. The method of claim 9 , wherein the first, second, third or fourth dopants comprise a doped glass.

16. An integrated circuit device, comprising:
a silicon substrate;
an interconnect layer comprising interconnect structures and an interlayer dielectric; and
one or more semiconductor devices, located between the silicon substrate and the interconnect layer, each of the one or more semiconductor devices comprising:
a first fin located on the silicon substrate, the first fin comprising a first material, a second material, a third material, and a fourth material, wherein the first fin has a first portion and a second portion, wherein the first portion includes the first material, the second material, the third material, and the fourth material, wherein the second portion includes the first material and the second material, wherein the first material of the second portion is materially contiguous with the first material of the first portion, wherein the second material of the second portion is materially contiguous with the second material of the first portion, and wherein:
the first material is located between the second material and the silicon substrate,
the second material is located between the third material and the first material,
the third material is located between the fourth material and the second material,
the first material and the third material are formed from a first type of extrinsic semiconductor, and
the second material and the fourth material are formed from a second type of extrinsic semiconductor, the second type different from the first type,

a second fin located on the silicon substrate, laterally separated from the first fin, wherein the second fin has a material that is materially contiguous with at least one of the first material, the second material, the third material, or the fourth material;
a first conductive contact located on the fourth material; and
a second conductive contact located on the second material of the second portion.

17. The integrated circuit device of claim 16 , wherein the one or more semiconductor devices is included in electrostatic

Assignees

• Hafez Walid M
• Jan Chia Hong
• Intel Corp

Inventors

• Hafez Walid M
• Jan Chia-Hong

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10D18/00 Primary

  Thyristors · CPC title

• H01L29/66363

  Electricity · mapped topic

• H01L27/0262

  Electricity · mapped topic