Semiconductor chip flexibly applied to various routing structures and semiconductor chip module using the same

Patent metadata

Field	Value
Publication number	US-10002850-B2
Application number	US-201615221920-A
Country	US
Kind code	B2
Filing date	Jul 28, 2016
Priority date	Apr 28, 2016
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A semiconductor chip may include a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip may include a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip may include a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a semiconductor substrate having a front surface and a rear surface which faces away from the front surface;
a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines which are formed in the fixed metal layer;
a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and an other surface which faces away from the one surface, and having second metal lines which are formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface; and
external connection members formed over the other surface of the configurable metal layer including the second metal lines,
wherein the second metal lines of the configurable metal layer are respectively coupled to the predetermined positions and are configured to connect all of the external connection members located at the predetermined positions to a respective first metal line,
wherein all of the predetermined positions are respectively coupled to the external connection members when all the external connection members are microbumps; and only some of the predetermined positions, less than all of the predetermined positions, are coupled to the external connection members when all the external connection members are solder bumps; and
wherein a diameter of each of the solder bumps is larger than a diameter of each of the microbumps.

2. The semiconductor chip according to claim 1 , wherein the semiconductor substrate comprises a plurality of TSVs (through-silicon vias) which are formed to pass through the front surface and the rear surface of the semiconductor substrate, and are electrically connected with the first metal lines of the fixed metal layer.

3. The semiconductor chip according to claim 2 , wherein the TSVs are formed to be respectively connected with the first metal lines which are arranged on the same vertical lines as the TSVs.

4. The semiconductor chip according to claim 1 , wherein the fixed metal layer including the first metal lines has a multi-layered wiring line structure.

5. The semiconductor chip according to claim 1 , further comprising:
I/O buffers formed in the fixed metal layer to be electrically connected with some second metal lines of the configurable metal layer.

6. The semiconductor chip according to claim 5 , further comprising:
connection lines formed in the configurable metal layer to electrically connect the I/O buffers and the second metal lines.

7. The semiconductor chip according to claim 1 , wherein, one group includes four first metal lines, the configurable metal layer is formed such that the second metal lines are connected with only first metal lines positioned first and third from a left end when viewed in a cross-section and respectively extend vertically.

8. The semiconductor chip according to claim 1 , wherein, one group includes four first metal lines, the configurable metal layer is formed such that the second metal lines are connected with only first metal lines positioned first and third from a left end when viewed in a cross-section and extend to cross each other.

9. The semiconductor chip according to claim 1 , wherein, one group includes four first metal lines, the configurable metal layer is formed such that two second metal lines are connected with first metal lines positioned first and second from a left end when viewed in a cross-section and extend to cross each other and the other two second metal lines are connected with first metal lines positioned third and fourth from the left end when viewed in the cross-section and extend to cross each other.

10. The semiconductor chip according to claim 1 , wherein, one group includes four first metal lines, the configurable metal layer is formed such that three second metal lines have at least one end which are respectively connected with first metal lines positioned first, second and third from a left end when viewed in a cross-section and the other ends which are arranged on the same vertical lines as first metal lines positioned second, third and fourth, and that one second metal line connected at one end with the first metal line positioned fourth has the other end which is arranged on the same vertical line as the first metal line positioned first.

11. A semiconductor chip module comprising:
a semiconductor chip including a semiconductor substrate having a front surface and a rear surface which faces away from the front surface, a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines which are formed in the fixed metal layer, and a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and an other surface which faces away from the one surface, and having second metal lines which are formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and the other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface;
one or more additional semiconductor chips stacked over the semiconductor chip, and each having the same structure as the semiconductor chip; connection members interposed between the semiconductor chip and a lowermost additional semiconductor chip and between the one or more additional semiconductor chips, and physically and electrically connecting the semiconductor chip and the one or more additional semiconductor chips; and external connection members formed over the other surface of the configurable metal layer of the semiconductor chip, which includes the second metal lines, wherein the second metal lines of the configurable metal layer are respectively coupled to the predetermined positions and are configured to connect all of the external connection members located at the predetermined positions to a respective first metal line,
wherein all of the predetermined positions are respectively coupled to the external connection members when all the external connection members are microbumps; and only some of the predetermined positions, less than all of the predetermined positions, are coupled to the external connection members when all the external connection members are solder bumps; and
wherein a diameter of each of the solder bumps is larger than a diameter of each of the microbumps.

12. The semiconductor chip module according to claim 11 , wherein each of semiconductor substrates of the semiconductor chip and the one or more additional semiconductor chips comprises a plurality of TSVs which are formed to pass through the front surface and the rear surface of the respective semiconductor substrates, and are electrically connected with the first metal lines of the fixed metal layer.

13. The semiconductor chip module according to claim 12 , wherein the connection members are formed to electrically connect the TSVs of the semiconductor chip and the second metal lines of the lowermost additional semiconductor chip and electrically connect the TSVs of an underlying additional semiconductor chip and the second metal lines of an overlying additional semiconductor chip.

14. The semiconductor chip module according to claim 11 , wherein the fixed metal layer has a multi-layered wiring line structure

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang Eun
• Ko Eun
• Park Yong Jae

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title