Structure for establishing interconnects in packages using thin interposers

Patent metadata

Field	Value
Publication number	US-10002835-B2
Application number	US-201715427156-A
Country	US
Kind code	B2
Filing date	Feb 8, 2017
Priority date	Nov 19, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

First claim

What is claimed is:

1. A semiconductor device, comprising
a substrate having a top surface;
a splice interposer having a first plurality of pillars formed on a bottom surface thereof, wherein the splice interposer is attached to the top surface of the substrate through the first plurality of pillars;
a first semiconductor die having a second plurality of pillars and a third plurality of pillars formed a bottom surface of the first semiconductor die, wherein the first semiconductor die is attached to the top surface of the substrate through the second plurality of pillars and to a top surface of the splice interposer through the third plurality of pillars, wherein the second plurality of pillars have a first uniform height and the third plurality of pillars have a second uniform height that is smaller than the first uniform height; and
a second semiconductor die having a fourth plurality of pillars formed on a bottom surface of the second semiconductor, wherein the second semiconductor die is attached to the top surface of the splice interposer through the fourth plurality of pillars,
wherein the first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

2. The semiconductor device of claim 1 , wherein the second plurality of pillars are formed at a central portion of the bottom surface of the first semiconductor die and the third plurality of pillars are formed at a peripheral portion of the bottom surface of the first semiconductor.

3. The semiconductor device of claim 1 , wherein the first semiconductor die comprises at least one of a CPU and a GPU and the second semiconductor die comprises at least one of a HBM, an optical I/O and an additional CPU or GPU.

4. The semiconductor device of claim 1 , wherein the top surface of the substrate and the top surface of the splice interposer are planarized.

5. The semiconductor device of claim 1 , wherein the first to fourth plurality of pillars comprise at least one stacked pillar formed on a corresponding surface of the first semiconductor die, the second semiconductor die or the splice interposer,
wherein the stacked pillar comprises a first conductor layer formed on the corresponding surface, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer and a second solder layer formed on the second conductor layer.

6. The semiconductor device of claim 5 , wherein the first conductor layer and the second conductor layer are formed from Cu,
wherein the first solder layer has a melting temperature lower than the melting temperature of Cu, and
wherein the first solder layer has a solidification temperature lower than the solidification temperature of the second solder layer.

7. The semiconductor device of claim 6 , wherein a first Ni layer is provided between the first conductor layer and the first solder layer and a second Ni layer is provided between the second conductor layer and the first solder layer,
wherein the first solder layer comprises a circumferential portion extending beyond the circumference of the first Ni layer and the second Ni layer, and
wherein, when viewed through a cross section view, the circumferential portion of the first solder layer is substantially half-spherical to at least partially cover a side surface of the first Ni layer and a side surface of the second Ni layer.

8. A stacked pillar used to interconnect a first semiconductor die and a second semiconductor die, comprising:
a first conductor layer formed on a surface of the first semiconductor die;
a first solder layer formed on the first conductor layer;
a second conductor layer formed on the first solder layer; and
a second solder layer formed on the second conductor layer, wherein the second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor,
wherein the first conductor layer and the second conductor layer are formed from Cu,
wherein the first solder layer has a melting temperature lower than the melting temperature of Cu,
wherein the first solder layer has a solidification temperature lower than the solidification temperature of the second solder layer,
wherein a first Ni layer is provided between the first conductor layer and the first solder layer and a second Ni layer is provided between the second conductor layer and the first solder layer,
wherein the first solder layer comprises a circumferential portion extending beyond the circumference of the first Ni layer and the second Ni layer, and
wherein, when viewed from a sectional perspective of the stacked pillar, the circumferential portion of the first solder layer is substantially half-spherical to at least partially cover a side surface of the first Ni layer and a side surface of the second Ni layer.

Assignees

• Globalfoundries Inc

Inventors

• Fasano Benjamin V
• Cranmer Michael S
• Indyk Richard F
• Cox Harry
• Sakuma Katsuyuki
• Perfecto Eric D

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07253

  changes in shapes · CPC title