On-chip combined hot carrier injection and bias temperature instability monitor

Patent metadata

Field	Value
Publication number	US-10002810-B2
Application number	US-201514750748-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Methods and circuits for monitoring circuit degradation include measuring degradation in a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation. The measured degradation for the plurality of test oscillators is extrapolated to determine a bias temperature instability (BTI) contribution to the measured degradation. The BTI contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value.

First claim

The invention claimed is:

1. A method for monitoring circuit degradation, comprising:
measuring degradation in a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation;
extrapolating from the measured degradation for the plurality of test oscillators to determine a bias temperature instability (BTI) contribution to the measured degradation;
subtracting the BTI contribution from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value.

2. The method of claim 1 , wherein the plurality of test oscillators vary according to oscillator frequency.

3. The method of claim 2 , wherein each test oscillator comprises a different number of inverters to provide a respective oscillator frequency.

4. The method of claim 1 , wherein the plurality of test oscillators vary according to capacitive load.

5. The method of claim 4 , wherein each test oscillator comprises a same number of inverters interspersed by a respective capacitive load.

6. The method of claim 1 , wherein the plurality of test oscillators vary according to channel length.

7. The method of claim 6 , wherein each test oscillator comprises a different number of inverters, with the inverters of each respective test oscillator having a different channel length, such that each of the plurality of test oscillators have a same frequency.

8. The method of claim 1 , wherein measuring degradation in the plurality of test oscillators comprises:
measuring first frequency information for the plurality of test oscillators;
measuring second frequency information for a reference oscillator;
comparing the first frequency information to the second timing information to determine a level of degradation for each of the plurality of test oscillators.

9. A system for monitoring circuit degradation, comprising:
a counter module configured to collect timing information from a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation; and
a fit module configured to determine a measurement of degradation for each test oscillator based on the timing information, to extrapolate from the measured degradation for the plurality of test oscillators to determine a bias temperature instability (BTI) contribution to the measured degradation, and to subtract the BTI contribution from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value.

10. The system of claim 9 , wherein the plurality of test oscillators vary according to oscillator frequency.

11. The system of claim 10 , wherein each test oscillator comprises a different number of inverters to provide a respective oscillator frequency.

12. The system of claim 9 , wherein the plurality of test oscillators vary according to capacitive load.

13. The system of claim 12 , wherein each test oscillator comprises a same number of inverters interspersed by different capacitive loads.

14. The system of claim 9 , wherein the plurality of test oscillators vary according to channel length.

15. The system of claim 14 , wherein each test oscillator comprises a different number of inverters, with the inverters of each respective test oscillator having a different channel length, such that each of the plurality of test oscillators have a same frequency.

16. The system of claim 9 , wherein the counter module is further configured to collect frequency information from a reference oscillator and wherein the fit module is configured to determine a measurement of degradation by comparing the frequency information from the plurality of test oscillators to the frequency information for the reference oscillator to determine a level of degradation for each of the plurality of test oscillators.

17. An on-chip test circuit, comprising:
a reference oscillator that is powered on only during tests;
a plurality of test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation;
a reference counter that provides timing information for the reference oscillator; and
a plurality of test counters that each provide timing information for a respective test ring oscillator.

18. The on-chip test circuit of claim 17 , wherein the plurality of test oscillators vary according to frequency and each test oscillator comprises a different number of inverters to provide a respective oscillator frequency.

19. The on-chip test circuit of claim 17 , wherein the plurality of test oscillators vary according to capacitive load and each test oscillator comprises a same number of inverters interspersed by a respective capacitive load.

20. The on-chip test circuit of claim 17 , wherein the plurality of test oscillators vary according to channel length and each test oscillator comprises a different number of inverters, with the inverters of each respective test oscillator having a different channel length, such that the plurality of test oscillators have a same frequency.

Assignees

• IBM

Inventors

• Jenkins Keith A
• Linder Barry

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• H01L22/34 Primary

  Electricity · mapped topic