Interrupt-controlled direct memory access peripheral data transfer

Patent metadata

Field	Value
Publication number	US-10002089-B2
Application number	US-201514939062-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Nov 12, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.

First claim

What is claimed is:

1. A method comprising:
transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral;
executing an interrupt service routine prologue in response to completion of the transferring of peripheral data;
executing a peripheral interrupt service routine after executing the interrupt service routine prologue; and
executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including negating an interrupt status flag associated with the interrupt request.

2. The method, as recited in claim 1 , further comprising:
providing a base address and a transfer trigger to initiate the transferring of the peripheral data.

3. The method, as recited in claim 1 , wherein executing the interrupt service routine includes executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.

4. The method, as recited in claim 1 , further comprising:
invalidating contents of the peripheral cache in response to the interrupt status flag being negated.

5. The method, as recited in claim 1 , further comprising:
receiving the interrupt request from the peripheral,
wherein the transferring is further in response to a peripheral direct memory access caching flag indicating the peripheral is direct-memory-access-cached.

6. A method comprising:
transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral;
executing an interrupt service routine prologue in response to completion of the transferring of peripheral data;
receiving a second interrupt request from a second peripheral; and
in response to a second peripheral direct memory access caching flag indicating the second peripheral is not direct-memory-access-cached:
executing the interrupt service routine prologue,
executing a peripheral interrupt service routine including accessing peripheral data from the second peripheral via the peripheral cache, and
executing an interrupt service routine epilogue after executing the peripheral interrupt service routine.

7. The method, as recited in claim 1 , wherein executing the peripheral interrupt service routine includes maintaining coherency of the peripheral cache with the peripheral.

8. The method, as recited in claim 1 , wherein the peripheral cache is a write-through cache.

9. A method comprising:
transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral;
executing an interrupt service routine prologue in response to completion of the transferring of peripheral data; and
in response to a peripheral direct memory access caching flag indicating the peripheral is direct-memory-access-cached:
triggering the transferring of the peripheral data and providing a base address for the transferring,
signaling completion of the transferring to trigger executing the interrupt service routine epilogue,
executing a peripheral interrupt service routine after executing the interrupt service routine prologue, and
executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including negating an interrupt status flag and invalidating peripheral cache entry.

10. A method comprising:
in response to an interrupt request from a peripheral and the peripheral being direct memory access cached:
transferring peripheral data from the peripheral to a write-through peripheral cache using direct memory access; and
executing an interrupt service routine prologue by a processor in response to an indication of peripheral data transfer completion; and

in response to the interrupt request from the peripheral and the peripheral not being direct memory access cached:
executing an interrupt service routine prologue;
executing a peripheral interrupt service routine by the processor after execution of the interrupt service routine prologue, wherein executing the peripheral interrupt service routine includes accessing of peripheral data from the peripheral via the write-through peripheral cache.

11. The method, as recited in claim 10 , wherein the processor executes instructions at a rate at least an order of magnitude faster than a read access rate of the peripheral.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Robertson Alistair Paul
• Maiolani Mark
• Moran Robert Freddie

Classifications

• G06F2212/656

  Address space sharing · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/34 Primary

  with priority control · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title