Static memory cell capable of balancing bit line leakage currents
US-10410687-B2 · Sep 10, 2019 · US
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Zhou Keji patents
Zhou Keji is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Zhou Keji |
| Total patents | 6 |
| First publication | Aug 24, 2017 |
| Latest publication | Sep 10, 2019 |
Notable patents
Publications ranked by popularity score, then publication date.
Static memory cell capable of balancing bit line leakage currents
US-2019206484-A1 · Jul 4, 2019 · US
Replica bit-line control circuit
US-9886206-B1 · Feb 6, 2018 · US
Static RAM for differential power analysis resistance
US-9886999-B2 · Feb 6, 2018 · US
Replica Bit-Line Control Circuit
US-2018024758-A1 · Jan 25, 2018 · US
Static ram for differential power analysis resistance
US-2017243636-A1 · Aug 24, 2017 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Univ Ningbo | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/419 | 6 |
| G11C11/418 | 4 |
| G11C7/227 | 4 |
| G11C7/12 | 4 |
| G11C11/417 | 2 |