Wafer level multi form factor die singulation
US-2026096368-A1 · Apr 2, 2026 · US
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Lopez Albert S patents
Lopez Albert S is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lopez Albert S |
| Total patents | 6 |
| First publication | Sep 12, 2019 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Carrier for microelectronic assemblies having direct bonding
US-2022199453-A1 · Jun 23, 2022 · US
TSV-less die stacking using plated pillars/through mold interconnect
US-11296052-B2 · Apr 5, 2022 · US
Flexible packaging for a wearable electronic device
US-10820437-B2 · Oct 27, 2020 · US
Tsv-less die stacking using plated pillars/through mold interconnect
US-2020212012-A1 · Jul 2, 2020 · US
Flexible packaging for a wearable electronic device
US-2019281717-A1 · Sep 12, 2019 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/00 | 3 |
| H10W70/635 | 3 |
| H10W70/68 | 3 |
| H10W90/722 | 2 |
| H10W90/24 | 2 |