Method for evaluating atomic vacancy in surface layer of silicon wafer and apparatus for evaluating the same
US-2016258908-A1 · Sep 8, 2016 · US
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Goto Terutaka patents
Goto Terutaka is listed as an inventor on 1 patent in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Goto Terutaka |
| Total patents | 1 |
| First publication | Sep 8, 2016 |
| Latest publication | Sep 8, 2016 |
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Major assignees
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| Assignee | Patents |
|---|---|
| Univ Niigata | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10P74/203 | 1 |
| G01N29/2462 | 1 |
| G01N2291/2697 | 1 |
| G01N29/2437 | 1 |
| G01N2291/0423 | 1 |