Calibration for surgical navigation
US-2026041498-A1 · Feb 12, 2026 · US
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Cohen Elazar patents
Cohen Elazar is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Cohen Elazar |
| Total patents | 24 |
| First publication | Jul 19, 2018 |
| Latest publication | Feb 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Detection of heat treated markings on a wooden pallet
US-2026004415-A1 · Jan 1, 2026 · US
Load balancing and networking policy performance by a packet processing pipeline
US-12489710-B2 · Dec 2, 2025 · US
Calibration for surgical navigation
US-12446971-B2 · Oct 21, 2025 · US
Detection of heat treated markings on a wooden pallet
US-12430743-B2 · Sep 30, 2025 · US
Sideband interface using CQEs
US-2025286828-A1 · Sep 11, 2025 · US
Network path state detection
US-2025286810-A1 · Sep 11, 2025 · US
Load balancing among output ports
US-12381824-B2 · Aug 5, 2025 · US
Hash-table lookup with controlled latency
US-12323328-B2 · Jun 3, 2025 · US
Flexible scheme for adding rules to a NIC pipeline
US-12218840-B2 · Feb 4, 2025 · US
Recent patents
Latest publications not already listed above.
Processing of packet fragments
US-2024334245-A1 · Oct 3, 2024 · US
Calibration for surgical navigation
US-2024216072-A1 · Jul 4, 2024 · US
Network interface device look-up operations
US-2024031289-A1 · Jan 25, 2024 · US
Concurrent electrophoretic deposition of membrane-electrode-assembly
US-2023155104-A1 · May 18, 2023 · US
Method and apparatus to aggregate objects to be stored in a memory to optimize the memory bandwidth
US-2023129107-A1 · Apr 27, 2023 · US
Detection of heat treated markings on a wooden pallet
US-2023112603-A1 · Apr 13, 2023 · US
Load balancing and networking policy performance by a packet processing pipeline
US-2023109396-A1 · Apr 6, 2023 · US
Packet processing with per flow hash key selection
US-2023055703-A1 · Feb 23, 2023 · US
Control plane isolation
US-2022385534-A1 · Dec 1, 2022 · US
Dynamic allocation of cache resources
US-2022043753-A1 · Feb 10, 2022 · US
Load balancing among output ports
US-2021328929-A1 · Oct 21, 2021 · US
3D micro-battery on 3D-printed substrate
US-10826126-B2 · Nov 3, 2020 · US
Hash-table lookup with controlled latency
US-2020136971-A1 · Apr 30, 2020 · US
3D Micro-Battery on 3D-Printed Substrate
US-2018205113-A1 · Jul 19, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 13 |
| Chep Technology Pty Ltd | 3 |
| Univ Ramot | 3 |
| Nuvasive Inc | 3 |
| Mellanox Technologies Ltd | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L45/7453 | 4 |
| H04L47/125 | 4 |
| H04L45/74591 | 3 |
| G06T2207/20132 | 3 |
| G06T7/0004 | 3 |