Memory devices having signal routing structures at bonding interfaces
US-2024404976-A1 · Dec 5, 2024 · US
Electricity
Electricity · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H01L24/03 |
| Official title | — |
| Display label | Electricity (mapped technology topic) |
| Total patents | 5,332 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 367 |
| 2016 | 435 |
| 2017 | 568 |
| 2018 | 527 |
| 2019 | 540 |
| 2020 | 542 |
| 2021 | 512 |
| 2022 | 439 |
| 2023 | 450 |
| 2024 | 438 |
| 2025 | 437 |
| 2026 | 77 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device manufacturing method and semiconductor device manufactured using the same
US-2024395745-A1 · Nov 28, 2024 · US
Device structure and methods of forming the same
US-2024371920-A1 · Nov 7, 2024 · US
Conductive barrier direct hybrid bonding
US-2024243085-A1 · Jul 18, 2024 · US
Chip package structure and method for preparing chip package structure
US-2024178167-A1 · May 30, 2024 · US
Methods for forming metal gapfill with low resistivity
US-2024088071-A1 · Mar 14, 2024 · US
Wafer-level package including under bump metal layer
US-11862589-B2 · Jan 2, 2024 · US
Process for realizing a connecting structure
US-9224704-B2 · Dec 29, 2015 · US
Semiconductor device including passivation layer encapsulant
US-9214385-B2 · Dec 15, 2015 · US
Method of making a die with recessed aluminum die pads
US-9209078-B2 · Dec 8, 2015 · US
Electronic device packages having bumps and methods of manufacturing the same
US-9209146-B2 · Dec 8, 2015 · US
Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
US-2015348922-A1 · Dec 3, 2015 · US
Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch
US-9202713-B2 · Dec 1, 2015 · US
Conductor design for integrated magnetic devices
US-2015340338-A1 · Nov 26, 2015 · US
Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate
US-9196562-B2 · Nov 24, 2015 · US
Semiconductor Device Having Solderable and Bondable Electrical Contact Pads
US-2015333023-A1 · Nov 19, 2015 · US
Semiconductor device and method for manufacturing the same
US-2015333024-A1 · Nov 19, 2015 · US
Semiconductor chip having different conductive pad widths and method of making layout for same
US-2015318249-A1 · Nov 5, 2015 · US
Embedding thin chips in polymer
US-9171794-B2 · Oct 27, 2015 · US
Semiconductor device having a trace comprises a beveled edge
US-9171793-B2 · Oct 27, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H01L24/03?
- CPC H01L24/03 is the Cooperative Patent Classification code for “Electricity.”
- How many patents are filed under CPC H01L24/03 (Electricity)?
- Our database includes 5,332 publications tagged with this CPC code.
- Is patent activity under CPC H01L24/03 growing?
- Publication counts under this code: 438 in 2024 vs 437 in 2025 (latest complete years).