Apparatus and method for making a secured substrate
US-2024355722-A1 · Oct 24, 2024 · US
Electricity
Electricity · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H01L2225/06572 |
| Official title | — |
| Display label | Electricity (mapped technology topic) |
| Total patents | 980 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 52 |
| 2016 | 132 |
| 2017 | 148 |
| 2018 | 121 |
| 2019 | 115 |
| 2020 | 101 |
| 2021 | 62 |
| 2022 | 69 |
| 2023 | 59 |
| 2024 | 57 |
| 2025 | 54 |
| 2026 | 10 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device and method of integrating power module with interposer and opposing substrates
US-2024304603-A1 · Sep 12, 2024 · US
Dynamic random-access memory in a molding beneath a die
US-2024113033-A1 · Apr 4, 2024 · US
Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
US-9484279-B2 · Nov 1, 2016 · US
Package-on-package semiconductor device
US-2016284669-A1 · Sep 29, 2016 · US
Method of embedding wlcsp components in e-wlb and e-plb
US-2016276325-A1 · Sep 22, 2016 · US
Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon
US-9418978-B2 · Aug 16, 2016 · US
Semiconductor package and method of manufacturing the same
US-2016071824-A1 · Mar 10, 2016 · US
Method for producing a wafer provided with chips
US-9224630-B2 · Dec 29, 2015 · US
Microelectronic package with consolidated chip structures
US-2015371968-A1 · Dec 24, 2015 · US
Electronic device
US-2015364428-A1 · Dec 17, 2015 · US
Integrated inductor and integrated inductor fabricating method
US-9214511-B2 · Dec 15, 2015 · US
Method of Forming Package-On-Package (PoP) Structure
US-2015357320-A1 · Dec 10, 2015 · US
Chip stacked package structure and electronic device
US-2015357307-A1 · Dec 10, 2015 · US
Package-on-package semiconductor device
US-2015357319-A1 · Dec 10, 2015 · US
Package Structure and Methods of Forming the Same
US-2015357309-A1 · Dec 10, 2015 · US
Semiconductor device
US-2015357310-A1 · Dec 10, 2015 · US
Three dimensional integrated circuits stacking approach
US-9209156-B2 · Dec 8, 2015 · US
Semiconductor devices compatible with mono-rank and multi-ranks
US-9209160-B2 · Dec 8, 2015 · US
Stackable multi-chip package system
US-9202776-B2 · Dec 1, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H01L2225/06572?
- CPC H01L2225/06572 is the Cooperative Patent Classification code for “Electricity.”
- How many patents are filed under CPC H01L2225/06572 (Electricity)?
- Our database includes 980 publications tagged with this CPC code.
- Is patent activity under CPC H01L2225/06572 growing?
- Publication counts under this code: 57 in 2024 vs 54 in 2025 (latest complete years).