Memory load and arithmetic load unit (ALU) fusing

Patent metadata

Field	Value
Publication number	US-10275217-B2
Application number	US-201715612963-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Mar 14, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

First claim

What is claimed is:

1. A load unit comprising:
a load circuit configured to load at least one piece of data from a memory;
an alignment circuit configured to align the data to generate an aligned data;
a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand; and
wherein the load unit is configured to:
determine whether, an active instruction is associated with the predetermined mathematical operation, and
in response to determining that the active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

2. The load unit of claim 1 , wherein the mathematical operation execution circuit comprises a plurality of substantially identical combinatorial logical circuits,
wherein each of the plurality of substantially identical combinatorial logical circuits is configured to perform substantially the same mathematical operation upon a respective version of the piece of data, wherein each of the respective versions of the piece of data include a one of a plurality of alignments of the piece of data.

3. The load unit of claim 2 , wherein the mathematical operation execution circuit comprises an alignment selector configured to select, based at least upon the alignment of the respective version of the piece of data, which output of the plurality of substantially identical combinatorial logical circuits is associated is the resultant.

4. The load unit of claim 1 , wherein the mathematical operation execution circuit is configured to:
select between a plurality of alignment variations of the piece of data, and
input a selected alignment variation of the piece of data to a combinatorial logical circuit; and
the combinatorial logic circuit is configured to generate the resultant by performing a mathematical operation upon, at least, the selected alignment variation of the piece of data.

5. The load unit of claim 1 , wherein the alignment circuit and the mathematical operation execution circuit are arranged in parallel.

6. The load unit of claim 1 , wherein the predetermined mathematical operation comprises addition.

7. The load unit of claim 1 , wherein the mathematical operation execution circuit is configured to generate the resultant with less latency than generating the aligned data, passing the aligned data to an execution unit that also performs the predetermined mathematical operation, and generating, by the execution unit, the execution unit's version of the resultant.

8. The load unit of claim 1 , wherein the active instruction that causes the load unit to bypass the alignment circuit indicates that both a load operation and the predetermined mathematical operation are to be performed.

9. The load unit of claim 1 , further comprising:
a pipeline management circuit is configured to indicate whether the active instruction is associated with the predetermined mathematical operation, wherein
the load unit is configured to, if the pipeline management circuit indicates that the active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit.

10. A system comprising:
a mathematical execution unit that includes combinatorial logical circuits and configured to perform a plurality of substantially identical logical operations based upon an instruction and at least one piece of data;
a combined load-store/mathematical unit configured to both:
load a piece of data from a memory, and
based upon an active instruction, perform a predetermined one of the plurality of substantially identical logical operations based upon the piece of data, wherein selection of the predetermined one of plurality of substantially logical operations is based, at least in part, upon an alignment of the piece of data; and

wherein the system is configured to:
determine whether the active instruction is at least associated with the predetermined one of the plurality of logical operations, and
in response to determining that the active instruction is at least associated with the predetermined one of the plurality of logical operations, assigning the instruction to be executed by the combined load-store/mathematical unit instead of the mathematical execution unit.

11. The system of claim 10 ,
wherein each of the plurality of substantially identical combinatorial logical circuits is configured to perform substantially the same mathematical operation upon a respective version of the piece of data, wherein each of the respective versions of the piece of data include a one of a plurality of alignments of the piece of data.

12. The system of claim 11 , wherein the combined load-store/mathematical unit comprises an alignment selector configured to select, based at least upon the alignment of the respective version of the piece of data, which output of the plurality of substantially identical combinatorial logical circuits is associated is a resultant.

13. The system of claim 10 , wherein the combined load-store/mathematical unit is configured to:
select between a plurality of alignment variations of the piece of data, and
input a selected alignment variation of the piece of data to a combinatorial logical circuit; and

the combinatorial logic circuit is configured to generate a resultant by performing a mathematical operation upon, at least, the selected alignment variation of the piece of data.

14. The system of claim 10 , wherein the mathematical operation comprises addition.

15. The system of claim 10 , wherein the combined load-store/mathematical unit is configured to generate a resultant with less latency than if the combined load-store/mathematical unit loaded the piece of data from a memory, passed the piece of data to the mathematical execution unit, and the mathematical execution unit generated the mathematical execution unit's version of the resultant.

16. The system of claim 10 , wherein the system is configured to:
determine whether the active instruction is associated with both a load operation and the predetermined one of the plurality of logical operations, and
in response to determining that the active instruction is associated with both a load operation and the predetermined one of the plurality of logical operations, assigning the instruction to be executed by the combined load-store/mathematical unit instead of the mathematical execution unit.

17. A method of employing a load unit comprising:
loading a piece of data from a memory;
determining, based at least in part upon an active instruction, whether to transfer the piece of data to an execution unit, or to generate, within the load unit, a resultant based upon the piece of data;
wherein if the piece of data is transferred to an execution unit, aligning the piece of data prior to transferring the piece of data; and
wherein if a resultant is generated by the load-store unit, generating a plurality of alignments of the piece of data and generating the resultant of a predetermined mathematical operation based upon the at least one of the plurality of alignments of the piece of data.

18. The method of claim 17 , wherein generating the resultant of comprises:
generating a plurality of resultant variations by performing the predetermined mathematical operation upon a plurality of alignment variations of the piece of data; and
selecting one of the plurality of resultant variations as the resultant of the predetermine

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gopal Rama S
• Kitchin Paul E
• Sundaram Karthik

Classifications

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F7/38

  Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation · CPC title