Method and device for checking a digital multiplier

Patent metadata

Field	Value
Publication number	US-9612796-B2
Application number	US-201414176785-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Feb 8, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A method for calculating an error signal that enables a diagnosis of the correctness of a product, determined by a first multiplier unit, of a first factor and a second factor, the error signal being determined by a difference formation unit as the difference of a sum logarithm and a product logarithm.

First claim

What is claimed is:

1. A method for determining an error in a first multiplier unit of an ASIC circuit of a safety critical system, the method comprising:
determining, via the first multiplier unit, a product of a first factor and a second factor;
determining, via a first logarithm formation unit, a product logarithm as a logarithm of an absolute value of the product from the first multiplier unit;
determining, via a summation unit, a sum logarithm from a sum of a first exponent and a second exponent and a mantissa logarithm; and
determining, via a difference formation unit, the error as a difference of the sum logarithm and the product logarithm;
wherein the mantissa logarithm is determined by a second logarithm formation unit as a logarithm of an absolute value of a mantissa product, the mantissa product being determined by a second multiplier unit as a product of a first approximated normalized mantissa and a second approximated normalized mantissa, the first approximated normalized mantissa being determined by a first normalizing unit as an approximation of a normalized mantissa of the floating-point representation of the first factor to a base, the first exponent being the exponent belonging to the base in a floating-point representation of the first factor; and
wherein the second approximated normalized mantissa is determined by a second normalizing unit as an approximated normalized mantissa of a floating-point representation of the second factor to the base, the second exponent being the exponent belonging to the base in the floating-point representation of the second factor,
wherein the product is recognized as false if the error exceeds or falls below a percent range relative to a correct product, and
wherein the error is in the first multiplier unit of the ASIC circuit of the safety critical system.

2. The method as recited in claim 1 , wherein the first approximated normalized mantissa is the approximation, limited to a first specifiable word width, of the normalized mantissa of the floating-point representation of the first factor.

3. The method as recited in claim 2 , wherein the first specifiable word width is smaller than a word width of the first factor.

4. The method as recited in claim 1 , wherein the second approximated normalized mantissa is the approximation, limited to a second specifiable word width, of the normalized mantissa of the floating-point representation of the second factor.

5. The method as recited in claim 4 , wherein the second specifiable word width is smaller than a word width of the second factor.

6. The method as recited in claim 4 , wherein the first specifiable word width is equal to the second specifiable word width.

7. The method as recited in claim 1 , wherein the product logarithm is determined as a logarithm to base 2 of the absolute value of the product, and the mantissa logarithm is determined as the logarithm to the base 2 of the absolute value of the mantissa product, and the base of the floating-point representation of the first factor and of the second factor is selected to be 2.

8. The method as recited in claim 1 , wherein the second logarithm formation unit determines the mantissa logarithm using Mitchell approximation.

9. The method as recited in claim 1 , wherein the first logarithm formation unit determines the product logarithm using Mitchell approximation.

10. The method as recited in claim 1 , wherein the product is not correct if one of: i) if the error is smaller than a known specifiable lower threshold value, or ii) if the error is greater than a known specifiable upper threshold value.

11. The method as recited in claim 1 , wherein a first sign of the first factor is determined, and a second sign of the second factor is determined, and a third sign of the product is determined, and wherein it is determined that the product is not correct if the product of the first sign and the second sign does not correspond to the third sign.

12. A device to determine an error in a first multiplier unit of an ASIC circuit of a safety critical system, comprising:
a hardware circuit including or a processor having a program for implementing the following:
a first normalizing unit;
a second normalizing unit;
a second multiplier unit;
a first logarithm formation unit;
a second logarithm formation unit;
a difference formation unit; and
a summation unit;

wherein the hardware circuit or the processor is configured to perform the following:
determining, via the first multiplier unit, a product of a first factor and a second factor;
determining, via the first logarithm formation unit, a product logarithm as a logarithm of an absolute value of the product from the first multiplier unit;
determining, via the summation unit, a sum logarithm from a sum of a first exponent and a second exponent and a mantissa logarithm; and
determining, via the difference formation unit, the error as a difference of the sum logarithm and the product logarithm;

wherein the mantissa logarithm is determined by the second logarithm formation unit as a logarithm of an absolute value of a mantissa product, the mantissa product being determined by a second multiplier unit as a product of a first approximated normalized mantissa and a second approximated normalized mantissa, the first approximated normalized mantissa being determined by the first normalizing unit as an approximation of a normalized mantissa of the floating-point representation of the first factor to a base, the first exponent being the exponent belonging to the base in a floating-point representation of the first factor;
wherein the second approximated normalized mantissa is determined by the second normalizing unit as an approximated normalized mantissa of the floating-point representation of the second factor to the base, the second exponent being the exponent belonging to the base in a floating-point representation of the second factor, and
wherein the product is recognized as false if it exceeds or falls below a percent range relative to a correct product, and
wherein the error is in the first multiplier unit of the ASIC circuit of the safety critical system.

Assignees

• Bosch Gmbh Robert

Inventors

• Uhl Alexander

Classifications

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F5/012 Primary

  in floating-point computations · CPC title

• G06F7/523

  Multiplying only · CPC title

• G06F11/0754

  by exceeding limits · CPC title

• G06F11/0706

  the processing taking place on a specific hardware platform or in a specific software environment · CPC title