Compute optimizations for neural networks using bipolar binary weight

Patent metadata

Field	Value
Publication number	US-11074072-B2
Application number	US-201916505012-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Apr 24, 2017
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

First claim

What is claimed is:

1. A compute apparatus comprising:
a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network, wherein the bipolar binary weight represents a weight value of one of positive one and negative one and the weight value is referenced via an index into a multi-bit register; and
an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

2. The compute apparatus as in claim 1 , wherein the bipolar binary weight is one of multiple weights within the multi-bit register.

3. The compute apparatus as in claim 2 , wherein the multiplier includes a sign flip unit to generate the intermediate product, the sign flip unit to flip the sign of the multi-bit input value for a bipolar weight value of negative one and pass through the multi-bit input value for a bipolar weight value of positive one.

4. The compute apparatus as in claim 3 , wherein the bipolar binary weight represents a weight value of negative one as a binary zero.

5. The compute apparatus as in claim 4 , wherein the multiplier includes a NOT gate between an input for the bipolar binary weight and the sign flip unit.

6. The compute apparatus as in claim 4 , wherein the sign flip unit has an active low activation input.

7. The compute apparatus as in claim 4 , wherein the sign flip unit includes an input for a weight index.

8. The compute apparatus as in claim 1 , additionally including an output register to store an output value of the single instruction.

9. The compute apparatus as in claim 1 , wherein the multi-bit input value has a power of two number of bits.

10. A method comprising:
decoding a single instruction specifying multiple operands, the operands including a multi-bit input value and a bipolar binary weight associated with a neural network, wherein the bipolar binary weight represents a weight value of one of positive one and negative one and the weight value is referenced via an index into a multi-bit register;
issuing the single instruction for execution within a compute unit of a general-purpose graphics processing unit; and
responsive to the execution of the single instruction, generating a result by performing a multiplication operation on the multi-bit input value based on the bipolar binary weight to generate an intermediate product and updating a value stored in an accumulator register by adding the intermediate product to the value stored in an accumulator register.

11. The method as in claim 10 , wherein the bipolar binary weight is one of multiple weights within the multi-bit register.

12. The method as in claim 11 , additionally comprising generating the intermediate product via a sign flip unit, wherein the sign flip unit is to flip the sign of the multi-bit input value for a bipolar weight value of negative one and pass through the multi-bit input value for a bipolar weight value of positive one.

13. The method as in claim 12 , wherein the bipolar binary weight represents a weight value of negative one as a binary zero.

14. The method as in claim 13 , wherein the sign flip unit includes an input for a weight index.

15. The method as in claim 13 , wherein the multi-bit input value has a power of two number of bits.

16. A data processing system comprising:
a general-purpose graphics processing unit comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network, an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the bipolar binary weight to generate an intermediate product, the bipolar binary weight represents a weight value of one of positive one and negative one, the weight value is referenced via an index into a multi-bit register, and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register; and
a memory coupled with the general-purpose graphics processing unit.

17. The data processing system as in claim 16 , wherein the bipolar binary weight is one of multiple weights within the multi-bit register.

18. The data processing system as in claim 17 , wherein the multiplier includes a sign flip unit to generate the intermediate product, the sign flip unit to flip the sign of the multi-bit input value for a bipolar weight value of negative one and pass through the multi-bit input value for a bipolar weight value of positive one.

19. The data processing system as in claim 18 , wherein the bipolar binary weight represents a weight value of negative one as a binary zero.

20. The data processing system as in claim 19 , wherein the multi-bit input value has a power of two number of bits.

Assignees

• Intel Corp

Inventors

• Nealis Kevin
• Yao Anbang
• Chen Xiaoming
• Ould-Ahmed-Vall Elmoustapha
• Baghsorkhi Sara S
• Nurvitadhi Eriko
• Vembu Balaji
• Galoppo Von Borries Nicolas C
• Barik Rajkishore
• Lin Tsung-Han
• Sinha Kamal

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/0895

  Weakly supervised learning, e.g. semi-supervised or self-supervised learning · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/098

  Distributed learning, e.g. federated learning · CPC title