Undercut insulating regions for silicon-on-insulator device
US-9214378-B2 · Dec 15, 2015 · US
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Haran Balasubramanian S patents
Haran Balasubramanian S holds 7 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 7 |
| Recent patents | 0 |
| First publication | Jan 6, 2015 |
| Latest publication | Dec 15, 2015 |
Filing trend
Year-over-year patent counts for this assignee.
Not enough yearly data to assess filing trend yet.
| Year | Patents |
|---|---|
| 2015 | 7 |
| Year | Patents |
|---|---|
| 2015 | 7 |
Recent patents
Latest publications where this party is an assignee.
Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
US-9093558-B2 · Jul 28, 2015 · US
CMOS with dual raised source and drain for NMOS and PMOS
US-9087741-B2 · Jul 21, 2015 · US
Shallow trench isolation structures
US-9059243-B2 · Jun 16, 2015 · US
SOI device with embedded liner in box layer to limit STI recess
US-8987070-B2 · Mar 24, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Undercut insulating regions for silicon-on-insulator device
US-9214378-B2 · Dec 15, 2015 · US
Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
US-9093558-B2 · Jul 28, 2015 · US
CMOS with dual raised source and drain for NMOS and PMOS
US-9087741-B2 · Jul 21, 2015 · US
Shallow trench isolation structures
US-9059243-B2 · Jun 16, 2015 · US
SOI device with embedded liner in box layer to limit STI recess
US-8987070-B2 · Mar 24, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10W10/181 | 4 |
| H10W10/061 | 4 |
| H10W10/17 | 4 |
| H10W10/014 | 4 |
| H10P90/1906 | 4 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 7 |