Semiconductor device

USRE50035E · US · E1

Patent metadata
FieldValue
Publication numberUS-RE50035-E
Application numberUS-200417688267-A
CountryUS
Kind codeE1
Filing dateMar 30, 2004
Priority dateMar 31, 2003
Publication dateJul 9, 2024
Grant dateJul 9, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

By stably separating a melting location of a fuse ( 3 ) from conductive layers ( 5 A, 5 B), reliable melting of the fuse ( 3 ) is enabled. A fuse ( 3 ) including a fuse body ( 3 A) and two pads ( 3 Ba, 3 Bb) connected by this and two conductive layers ( 5 A, 5 B) individually connected to the two pads ( 3 Ba, 3 Bb) are formed in a multilayer structure on a semiconductor substrate ( 1 ). A length of the fuse body ( 3 A) is defined so that the melting location of the fuse ( 3 ) becomes positioned in the fuse body ( 3 A) away from the region overlapped on the conductive layer ( 5 A or 5 B) when an electrical stress is applied between two conductive layers ( 5 A, 5 B) and the fuse ( 3 ) is melted.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising a fuse ( 3 ) having a fuse body ( 3 A) and two pads ( 3 Ba, 3 Bb) connected by the fuse body ( 3 A) and two conductive layers ( 5 A, 5 B) individually connected to two pads ( 3 Ba, 3 Bb), the above being formed inside a multilayer structure on a semiconductor substrate ( 1 ), characterized in that a length (L 1 ) of the fuse body ( 3 A) is defined so that the melting location of the fuse ( 3 ) becomes positioned in the fuse body ( 3 A) away from a region overlapped on the conductive layers ( 5 A, 5 B) when an electrical stress is applied between the two conductive layers ( 5 A, 5 B) to melt the fuse ( 3 ); and in at least one of the above two conductive layers ( 5 A, 5 B), a distance (D 4 ) from the contact regions ( 4 A, 4 B) connecting the conductive layers ( 5 A, 5 B) and the pads ( 3 Ba, 3 Bb) to edges of the pad ( 3 Ba, 3 Bb) contacting the fuse body ( 3 A) is 0.25 μm to 0.90 μm. 2. A semiconductor device comprising a fuse ( 3 ) including a conductive material in a multilayer structure on a semiconductor substrate ( 1 ), said fuse ( 3 ) having a fuse body ( 3 A) and two pads ( 3 Ba, 3 Bb) connected by the fuse body ( 3 A), conductive layers ( 5 A, 5 B) connected one by one to said two pads ( 3 Ba, 3 Bb), characterized in that, in at least one of the above two conductive layers ( 5 A, 5 B), a width (W 3 ) of the portions of the conductive layers ( 5 A, 5 B) including the contact regions ( 4 A, 4 B) with the pads ( 3 Ba, 3 Bb) is 6 μm to 14 μm. 3. A semiconductor device comprising: a fuse body ( 3 A) connected to a pad ( 3 Ba), said fuse body ( 3 A) including a fuse line ( 3 Aa) and two connections ( 3 Ab); an inter-layer insulating film ( 4 ) on said pad ( 3 Ba), an opening ( 4 A) through said inter-layer insulating film ( 4 ) exposing said pad ( 3 Ba); a conductive layer ( 5 A) on said inter-layer insulating film ( 4 ), said conductive layer ( 5 A) within said opening ( 4 A) being electrically connected to said pad ( 3 Ba), wherein at least one of the following is present: (a) the width (W 3 ) of said conductive layer ( 5 A) is 6 μm to 14 μm, (b) the distance (D 4 ) between said fuse line ( 3 Aa) and said opening ( 4 A) is 0.25 μm to 0.90 μm, (c) the length (L 1 ) of the fuse body ( 3 A) is 1.8 μm to 20 μm. 4. A semiconductor device as set forth in claim 3 , wherein the melting location of a fuse ( 3 ) becomes positioned in said fuse body ( 3 A) away from a region overlapped on said conductive layer ( 5 A) when an electrical stress to melt said fuse ( 3 ) is applied between said conductive layer ( 5 A) and another conductive layer ( 5 B). 5. A semiconductor device as set forth in claim 3 , wherein said width (W 3 ) of said conductive layer ( 5 A) is 6 μm to 14 μm. 6. A semiconductor device as set forth in claim 3 , wherein said distance (D 4 ) between said fuse line ( 3 Aa) and said opening ( 4 A) is 0.25 μm to 0.90 μm. 7. A semiconductor device as set forth in claim 3 , wherein said length (L 1 ) of the fuse body ( 3 A) is 1.8 μm to 20 μm. 8. A semiconductor device as set forth in claim 3 , wherein said width (W 3 ) is a dimension perpendicular to the direction of current flowing through a fuse ( 3 ). 9. A semiconductor device as set forth in claim 3 , wherein said length (L 1 ) is a dimension in the direction of current flowing through a fuse ( 3 ), said length (L 1 ) including the length (L 0 ) of said fuse line ( 3 Aa) and the lengths (L 2 ) of said two connections ( 3 Ab). 10. A semiconductor device as set forth in claim 3 , wherein another conductive layer ( 5 B) within another opening ( 4 A) through said inter-layer insulating film ( 4 ) is electrically connected to another pad ( 3 Bb), the distance (D 0 ) between said conductive layer ( 5 A) and said another conductive layer ( 5 B) is larger than said length (L 1 ). 11. A semiconductor device as set forth in claim 3 , wherein one of the connections ( 3 Ab) electrically connects said pad ( 3 Ba) with fuse line ( 3 Aa), said one of the connections ( 3 Ab) being between said pad ( 3 Ba) and said fuse line ( 3 Aa). 12. A semiconductor device as set forth in claim 3 , wherein each of said two connections ( 3 Ab) is wider than said fuse line ( 3 Aa). 13. A semiconductor device as set forth in claim 3 , wherein a connection ( 3 Ab) of said two connections ( 3 Ab) has a width that increases toward said pad ( 3 Ba). 14. A semiconductor device as set forth in claim 3 , wherein the width of the fuse body ( 3 A) is smaller than the width (W 3 ) of said pad ( 3 Ba). 15. A semiconductor device as set forth in claim 3 , wherein one of the two connections ( 3 Ab) electrically connects said pad ( 3 Ba) with said fuse line ( 3 Aa). 16. A semiconductor device as set forth in claim 15 , wherein another of the two connections ( 3 Ab) electrically connects another pad ( 3 Bb) with said fuse line ( 3 Aa). 17. A semiconductor device as set forth in claim 16 , wherein another conductive layer ( 5 B) within another opening ( 4 A) through said inter-layer insulating film ( 4 ) is electrically connected to said another pad ( 3 Bb), the distance (D 0 ) between said conductive layer ( 5 A) and said another conductive layer ( 5 B) is larger than said length (L 1 ). 18. A semiconductor device as set forth in claim 17 , wherein said length (L 1 ) is the distance between said pad ( 3 Ba) and said another pad ( 3 Bb). 19. A semiconductor device as set forth in claim 1 , wherein said fuse body (3A) comprises a fuse line (3Aa) and two connections (3Ab), and one of the connections (3Ab) electrically connects said pad (3Ba) with fuse line (3Aa), said one of the connections (3Ab) being between said pad (3Ba) and said fuse line (3Aa). 20. A semiconductor device as set forth in claim 1 , wherein said fuse body (3A) comprises a fuse line (3Aa) and two connections (3Ab), and each of said two connections (3Ab) is wider than said fuse line (3Aa). 21. A semiconductor device as set forth in claim 1 , wherein said fuse body (3A) including a fuse line (3Aa) and two connections (3Ab), and a connection (3Ab) of said two connections (3Ab) has a width that increases toward said pad (3Ba). 22. A semiconductor device as set forth in claim 20 , wherein a distance (D2) between the fuse line (3Aa) and the contact region (4A) is longer than a distance between contact region (4A) and other edges of the pad (3Ba, 3Bb), and the other edges are opposite side to the edges of the pad (3Ba, 3Bb) contacting the fuse body (3A). 23. A semiconductor device as set forth in claim 22 , wherein a distance (D3) between the fuse body (3A) and one (5A) of the two conductive layers (5A, 5B) has a positive value. 24. A semiconductor device as set forth in in claim 22 , wherein one of conductive layer (5B) within an opening (4A) through an inter-layer insulating film (4) is electrically connected to another pad (3Bb), the distance (D0) between said another conductive layer (5A) and said one of conductive layer (5B) is larger than said length (L1).

Assignees

Inventors

Classifications

  • H10W20/493Primary

    Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent USRE50035E cover?
By stably separating a melting location of a fuse ( 3 ) from conductive layers ( 5 A, 5 B), reliable melting of the fuse ( 3 ) is enabled. A fuse ( 3 ) including a fuse body ( 3 A) and two pads ( 3 Ba, 3 Bb) connected by this and two conductive layers ( 5 A, 5 B) individually connected to the two pads ( 3 Ba, 3 Bb) are formed in a multilayer structure on a semiconductor substrate ( 1 ). A l…
Who is the assignee on this patent?
Sony Group Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/493. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (E1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).