Testing circuits in stacked wafers using a connected electrode in the first wafer

Patent metadata

Field	Value
Publication number	US-RE47840-E
Application number	US-201514820325-A
Country	US
Kind code	E1
Filing date	Aug 6, 2015
Priority date	Feb 5, 2009
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

First claim

What is claimed is:

1. A method of testing a semiconductor device comprising;
providing a first wafer that comprises a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode;
providing a second wafer that comprises a second electrode penetrating the second wafer;
stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer;
probing a needle to the pad; and
supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

2. The method as claimed in claim 1 , wherein:
a circuit to be tested is included in the second wafer; and
the test signal is supplied to the circuit via the first electrode and the second electrode.

3. The method as claimed in claim 2 , wherein the second wafer further comprises a switch that is formed between the second electrode and the circuit.

4. The method as claimed in claim 3 , wherein the switch connects the second electrode with the circuit when the semiconductor device is under test.

5. The method as claimed in claim 1 , wherein the pad is connected directly with the first electrode.

6. The method as claimed in claim 5 , wherein the first wafer further comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.

7. The method as claimed in claim 1 , wherein the providing the second wafer comprises stacking a plurality of wafers, each of the plurality of wafers having a substantially identical structure.

8. The method as claimed in claim 1 , wherein the test signal is supplied to the needle, the test signal being supplied to the first electrode via the needle and the pad.

9. A method of producing a tested semiconductor device comprising:
forming a semiconductor device; and
testing the semiconductor device, the testing including:
stacking a first wafer onto a second wafer having the semiconductor device such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being coupled electrically with the semiconductor device; and
supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor device via the first electrode and the second electrode.

10. The method as claimed in claim 9 , wherein the second wafer comprises a switch that is formed between the second electrode and the semiconductor device.

11. The method as claimed in claim 10 , wherein the switch connects the second electrode with the semiconductor device when the semiconductor device is under test.

12. The method as claimed in claim 9 , wherein the testing further includes probing a needle to a pad that is formed on the first wafer and is coupled electrically with the first electrode.

13. The method as claimed in claim 12 , wherein the test signal is supplied to the needle, the test signal being supplied to the first electrode via the needle and the pad.

14. The method as claimed in claim 9 , wherein the first wafer comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.

15. The method as claimed in claim 9 , wherein the second wafer comprises a plurality of stacked wafers, each of the plurality of stacked wafers having a substantially identical structure.

16. A method of producing a semiconductor device comprising:
stacking a plurality of semiconductor chips, wherein each of the plurality of semiconductor chips has already been tested by a testing method, the testing method including;
stacking a first wafer onto a second wafer comprising the semiconductor chip such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being connected electrically with the semiconductor chip; and
supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor chip via the first electrode and the second electrode.

17. The method as claimed in claim 16 , wherein:
a circuit to be tested is included in the semiconductor chip of the second wafer; and
the test signal is supplied to the circuit via the first electrode and the second electrode.

18. The method as claimed in claim 17 , wherein:
the second wafer comprises a switch that is formed between the second electrode and the circuit; and
the switch connects the second electrode with the circuit when the circuit is under test.

19. The method as claimed in claim 16 , wherein the first wafer comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.

20. The method as claimed in claim 16 , wherein the second wafer comprises a plurality of stacked wafers, each of the plurality of stacked wafers having a substantially identical structure.

21. A semiconductor device comprising:
a plurality of chips each comprising:
a substrate having a first surface and a second surface opposite the first surface;
a plurality of through electrodes penetrating the substrate from the first surface to the second surface;
a test pad connected to a first through electrode of the plurality of through electrodes; and
a circuit to be tested;
wherein the plurality of chips are stacked and interconnected through the plurality of electrodes, and test access is provided to the circuit to be tested on each of the plurality of chips through the test pad on a first chip of the plurality of chips.

22. The semiconductor device as claimed in claim 21, wherein the test pad on the first chip is connected to the circuit to be tested on a second chip of the plurality of chips through a switch.

23. The semiconductor device as claimed in claim 22, wherein the switch connects the test pad on the first chip to the first through electrode on the first chip.

24. The semiconductor device as claimed in claim 22, wherein the switch connects the first through electrode on the second chip to the circuit to be tested on the second chip.

Assignees

• Ps4 Luxco Sarl
• Longitude Licensing Ltd

Inventors

• Riho Yoshiro

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title