Output buffer circuit and method for avoiding voltage overshoot

Patent metadata

Field	Value
Publication number	US-RE47743-E
Application number	US-201514800712-A
Country	US
Kind code	E1
Filing date	Jul 16, 2015
Priority date	Jan 27, 2010
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

First claim

What is claimed is:

1. An output buffer circuit for avoiding voltage overshoot, the output buffer circuit comprising:
an input stage circuit comprising a positive input terminal, for receiving an input voltage, and a negative input terminal, — the input stage circuit generating a current signal according to the input voltage;
an output bias circuit, coupled to the input stage circuit, for generating a dynamic bias according to the current signal;
an output stage circuit, coupled to the input stage circuit and the output bias circuit, comprising:
an output terminal, reversely coupled to the negative input terminal; and
at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage;
a clamp circuit, coupled to the input stage circuit, the output bias circuit and the output stage circuit, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range; and
a control unit controller, coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.

2. The output buffer circuit of claim 1 , wherein the control unit controller determines the output voltage reaches the steady state when the output buffer circuit receives the input voltage for a predefined time.

3. The output buffer circuit of claim 2 , wherein the control unit controller comprises:
a trigger circuit, for generating a trigger signal when the output buffer circuit receives the input voltage; and
a timer, coupled to the trigger circuit, for calculating the predefined time according to the trigger signal controlling the controller to switch a voltage for the clamp circuit to deactivate the clamp circuit after the timer receives the trigger signal and then counts the predefined time.

4. The output buffer circuit of claim 1 , wherein the control unit controller determines whether the output voltage reaches the steady state by detecting voltage difference between the output terminal and the positive input terminal after the output buffer circuit receives the input voltage.

5. The output buffer circuit of claim 4 , wherein the control unit controller comprises:
a voltage detection circuit, coupled to the positive input terminal and the output terminal, for detecting voltage levels of the positive input terminal and the output terminal; and
a comparison unit comparator, coupled to the voltage detection circuit, for determining the output voltage reaches the steady state when the voltage difference between the output terminal and the positive input terminal is smaller than a predefined value.

6. The output buffer circuit of claim 1 , wherein the clamp circuit comprises:
a first metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the output terminal, a gate second terminal coupled to an operating bias, and a drain third terminal; and
a second metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the drain third terminal of the first MOSFET, a gate second terminal coupled to the output bias circuit and the at least one output transistor, and a drain third terminal coupled to the gate second terminal of the second MOSFET;
wherein a level of the operating bias is switched by the control unit controller.

7. The output buffer circuit of claim 6 , wherein the control unit controller switches the operating bias to a first level to activate the clamp circuit when the output buffer circuit receives the input voltage, and switches the operating bias to a second level to deactivate the clamp circuit when the output voltage reaches the steady state.

8. The output buffer circuit of claim 7 , wherein the first MOSFET and the second MOSFET are both P type MOSFETs, for clamping the output voltage under a predefined high voltage level, and the second level is a power supply voltage.

9. The output buffer circuit of claim 7 , wherein the first MOSFET and the second MOSFET are both N type MOSFETs, for clamping the output voltage over a predefined low voltage level, and the second level is a ground voltage.

10. The output buffer circuit of claim 1 , wherein the input stage circuit is a differential input stage circuit having a rail-to-rail input range.

11. The output buffer circuit of claim 10 , wherein the input stage circuit comprises an N type metal-oxide-semiconductor (NMOS) differential input pair and a P type metal-oxide-semiconductor (PMOS) differential input pair.

12. The output buffer circuit of claim 1 , wherein the output bias circuit comprises a pair of head-to-tail connected complementary metal-oxide-semiconductor (CMOS) transistors.

13. The output buffer circuit of claim 1 , wherein the at least one output transistor form a class AB output stage circuit.

14. A method of avoiding voltage overshoot for an output buffer circuit, the output buffer circuit comprising an input stage circuit, an output stage circuit and a clamp circuit, the input stage circuit generating a current signal according to an input voltage, the output stage circuit generating an output voltage according to the current signal, the clamp circuit, coupled to the input stage circuit and the output stage circuit, for clamping the output voltage within a predefined range, the method comprising:
activating the clamp circuit when the input voltage is received;
starting to output the output voltage; and
deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.

15. The method of claim 14 , wherein the step of deactivating the clamp circuit when the output voltage reaches the steady state comprises:
determining the output voltage reaches the steady state when the input voltage is received for a predefined time.

16. The method of claim 14 , wherein the step of deactivating the clamp circuit when the output voltage reaches the steady state comprises:
determining whether the output voltage reaches the steady state by detecting voltage difference between the output voltage and the input voltage after the input voltage is received.

17. The method of claim 16 , wherein the step of determining whether the output voltage reaches the steady state comprises:
determining the output voltage reaches the steady state when the voltage difference between the output voltage and the input voltage is smaller than a predefined value.

18. An output buffer circuit for avoiding voltage overshoot, comprising:
an input circuit, configured to generate a current signal according to an input voltage; an output circuit, coupled to the input circuit and configured to generate an output voltage according to the current signal; a clamp circuit, coupled to the input circuit and the output circuit, and configured to clamp the output voltage within a predefined range; and a controller, configured to activate the clamp circuit when the input voltage is received and deactivate the clamp circuit to prevent a leakage current flowing through the clamp circuit when the output voltage reaches a steady state.

19. The output buffer circuit of claim 18, wherein the controller determines the output

Assignees

• Novatek Microelectronics Corp

Inventors

• Hsu Xie-Ren
• Chen Ji-Ting

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H03K5/2481

  with at least one differential stage · CPC title

• H03F2200/441

  Protection of an amplifier being implemented by clamping means · CPC title

• H03K19/018514 Primary

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title