Card and host device

Patent metadata

Field	Value
Publication number	US-RE47543-E
Application number	US-201715456857-A
Country	US
Kind code	E1
Filing date	Mar 13, 2017
Priority date	Nov 26, 2004
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

First claim

What is claimed is:

1. A memory card which is connectable to a host device, comprising:
a memory; and
a controller which connected to the memory, wherein the controller:
controls the memory,
receives from a host device a first command which includes from the host device the first command including a voltage identification section which has a bit pattern selected from two bit patterns, the bit pattern indicating voltages which the host device supports,
determines whether the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command, and
issues a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command when the memory card determines that the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command.

2. The memory card of claim 1 , wherein:
the memory card does not issue a response when the memory card determines that the memory card does not support the voltages indicated by the bit pattern in the voltage identification section of the first command.

3. The memory card of claim 1 , wherein:
the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and
the memory card issues the issued response which further includes an error detection section which has an error detection code and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

4. A host device which is connectable to a memory card, wherein the host device comprises:
a controller that:
reads and writes data from and into a memory card,
issues a first command which includes a voltage identification section which has a bit pattern selected from two bit patterns, the bit pattern indicating voltages which the host device supports,
performs initialization of the memory card when the host device receives a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command, and
terminates initialization of the memory card when the host device does not receive a response to the first command.

5. The host device of claim 4 , wherein:
the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and
the host device performs initialization of the memory card when the host device receives the response which from the memory card further includes an error detection section which has an error detection code which indicates no error and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

6. The host device of claim 4 , wherein:
the host device issues an initialization command which instructs the memory card to perform initialization when the host device receives a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command, and
the host device does not issue an initialization command which instructs the memory card to perform initialization is issued from the host device when the host device does not receive a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command from the memory card is received, and the initialization command is not issued when the response from the memory card is not received.

7. A memory card which is connectable to a host device, comprising:
a memory; and a controller connected to the memory, wherein the controller: controls the memory, receives a first command from the host device, the first command including a voltage identification section which has a bit pattern, the bit pattern indicating voltages which the host device supports, determines whether the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command, and issues a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command when the memory card determines that the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command.

8. The memory card of claim 7, wherein:
the memory card does not issue a response when the memory card determines that the memory card does not support the voltages indicated by the bit pattern in the voltage identification section of the first command.

9. The memory card of claim 7, wherein:
the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and the issued response further includes an error detection section which has an error detection code and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

10. A host device which is connectable to a memory card, wherein the host device comprises:
a controller that: reads and writes data from and into a memory card, issues a first command which includes a voltage identification section which has a bit pattern, the bit pattern indicating voltages which the host device supports, performs initialization of the memory card when the host device receives a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command, and terminates initialization of the memory card when the host device does not receive a response to the first command.

11. The host device of claim 10, wherein:
the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and the response from the memory card further includes an error detection section which has an error detection code which indicates no error and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

12. The host device of claim 10, wherein:
an initialization command which instructs the memory card to perform initialization is issued from the host device when the response from the memory card is received, and the initialization command is not issued when the response from the memory card is not received.

Assignees

• Toshiba Memory Corp

Inventors

• Fujimoto Akihisa

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• H04L1/0061

  Error detection codes · CPC title

• G06F2206/1014

  One time programmable [OTP] memory, e.g. PROM, WORM · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title