Method and controller for performing a sequence of commands

Patent metadata

Field	Value
Publication number	US-RE46201-E
Application number	US-201414243620-A
Country	US
Kind code	E1
Filing date	Apr 2, 2014
Priority date	Dec 30, 2009
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

First claim

What is claimed is:

1. A method for performing a sequence of commands, the method comprising:
performing in a controller in communication with a host and a flash memory device:
receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyzing the at least one bit to determine whether the at least one bit indicates that the command is a standalone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, performing the command; and
if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code.

2. The method of claim 1 3, wherein the flash memory device is organized into a plurality of planes, and wherein each command in the sequence of commands is performed in a different one of the plurality of planes.

3. The method of claim 1 , A method for performing a sequence of commands, the method comprising:
performing in a controller in communication with a host and a flash memory device:
receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyzing the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, performing the command; and
if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code wherein the sequence of commands comprises an atomic command sequence, and wherein the commands in the sequence of commands are performed together as a group.

4. The method of claim 1 3, wherein the sequence of commands comprise sequential commands with incremental addresses.

5. The method of claim 1 , A method for performing a sequence of commands, the method comprising:
performing in a controller in communication with a host and a flash memory device:
receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyzing the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, performing the command; and
if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code;

wherein the at least one bit is a single bit and wherein the single bit is one of a plurality of reserved address bits.

6. The method of claim 5 , wherein the single bit is one of a plurality of reserved address bits.

7. The method of claim 1 3, wherein at least one bit in a last command in the sequence of commands indicates that the command is a stand-alone command.

8. The method of claim 1 3, wherein the sequence of commands are received by the controller one command at a time.

9. The method of claim 8 further comprising sending a response back to the host either after the entire sequence of commands have been received or after each command in the sequence of commands has been received.

10. A controller for performing a sequence of commands, the controller comprising:
a first interface configured to transfer data between a host and the controller; a second interface configured to transfer data between the controller and a flash memory device; and circuitry operative to:
receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, perform the command; and
if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code.

11. The controller of claim 10 12, wherein the flash memory device is organized into a plurality of planes, and wherein each command in the sequence of commands is performed in a different one of the plurality of planes.

12. The controller of claim 10 , A controller for performing a sequence of commands, the controller comprising:
a first interface configured to transfer data between a host and the controller;
a second interface configured to transfer data between the controller and a flash memory device; and
circuitry operative to:
receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, perform the command; and
if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code;

wherein the sequence of commands comprises an atomic command sequence, and wherein the commands in the sequence of commands are performed together as a group.

13. The controller of claim 10 12, wherein the sequence of commands comprise sequential commands with incremental addresses.

14. The controller of claim 10 , wherein the at least one bit is a single bit.

15. The controller of claim 14 , A controller for performing a sequence of commands, the controller comprising:
a first interface configured to transfer data between a host and the controller;
a second interface configured to transfer data between the controller and a flash memory device; and
circuitry operative to:
receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands;
analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands;
if the at least one bit indicates that the command is a stand-alone command, perform the command; and
if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command cod

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Selinger Robert D
• Lin Gary
• Wang Chaoyang

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title