Method and controller for performing a copy-back operation

Patent metadata

Field	Value
Publication number	US-RE46013-E
Application number	US-201414243637-A
Country	US
Kind code	E1
Filing date	Apr 2, 2014
Priority date	Dec 30, 2009
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

First claim

What is claimed is:

1. A method for performing a copy-back command, the method comprising:
performing in a controller in communication with a host and at least one flash memory device:
receiving a source address and a copy-back read command from the host;
sending the source address and the copy-back read command to the at least one flash memory device, wherein in response to receiving the source address and the copy-back read command, the at least one flash memory device reads data from the source address and writes the data in a register in the at least one flash memory device;
receiving data stored at the source address and an error correction code associated with the data received from the at least one flash memory device;
determining that the error correction code indicates there is no error in the data;
modifying the received data, wherein the modification changes or adds information rather than corrects errors;
generating error correction code bits for modified data from the at least one flash memory device;
receiving a destination address and a copy-back program command from the host; and
sending the destination address, the modified data with the error correction code bits, and a program command to the at least one flash memory device.

2. The method of claim 1 , wherein the source address and destination address are for different planes of memory in one of the at least one flash memory device.

3. The method of claim 2 , wherein the register in the at least one flash memory device is shared between the different planes.

4. The method of claim 1 , wherein the source address and destination address are for different flash memory devices.

5. The method of claim 1 , wherein the source and destination addresses are physical addresses.

6. The method of claim 1 , wherein the source and destination addresses are logical addresses, and wherein the method further comprises using the controller to translate the logical addresses into physical addresses.

7. The method of claim 1 , wherein the controller communicates with the host over a first interface and communicates with the at least one flash memory device over a second interface.

8. The method of claim 7 , wherein at least one of the first and second interfaces comprises a NAND interface configured to transfer data using a NAND interface protocol.

9. The method of claim 1 , wherein the data is modified by the controller.

10. The method of claim 1 , wherein the data is modified by the host.

11. The method of claim 1 , wherein the modification changes or adds information to a header of the data.

12. The method of claim 11 , wherein the modification changes or adds information to one or more of the following in the header: a logical block address, a type field, a physical start address, a front end address block grouping, a run length of the data, and an endurance tag.

13. A method for performing a copy-back command, the method comprising:
performing in a controller in communication with a host and at least one flash memory device:
receiving a source address and a copy-back read command from the host;
sending the source address and the copy-back read command to the at least one flash memory device;
receiving data stored at the source address and an error correction code associated with the data;
determining that the error correction code indicates there is no error in the data;
modifying the data, wherein the modifying changes or adds information rather than corrects errors;
generating error correction code bits for modified data from the at least one flash memory device;
receiving a destination address and a copy-back program command from the host; and
sending the destination address, the modified data with the error correction code bits, and a program command to the at least one flash memory device;

wherein the source address and destination address are for different planes of memory in one of the at least one flash memory device; and
wherein the register in the at least one flash memory device is not shared between the different planes.

14. A controller comprising:
a first interface configured to transfer data between a host and the controller;
a second interface configured to transfer data between the controller and at least one flash memory device; and
circuitry operative to:
receive a source address and a copy-back read command from the host;
send the source address and the copy-back read command to the at least one flash memory device, wherein in response to receiving the source address and the copy-back read command, the at least one flash memory device reads data from the source address and writes the data in a register in the at least one flash memory device;
receive data stored at the source address and an error correction code associated with the data received from the at least one flash memory device;
determine that the error correction code indicates there is no error in the data;
modify the received data, wherein the modification changes or adds information rather than corrects errors;
generate error correction code bits for modified data from the at least one flash memory device;
receive a destination address and a copy-back program command from the host; and
send the destination address, the modified data with the error correction code bits, and a program command to the at least one flash memory device.

15. The controller of claim 14 , wherein the source address and destination address are for different planes of memory in one of the at least one flash memory device.

16. The controller of claim 15 , wherein the register in the at least one flash memory device is shared between the different planes.

17. The controller of claim 14 , wherein the source address and destination address are for different flash memory devices.

18. The controller of claim 14 , wherein the source and destination addresses are physical addresses.

19. The controller of claim 14 , wherein the source and destination addresses are logical addresses, and wherein the circuitry is further operative to use the controller to translate the logical addresses into physical addresses.

20. The controller of claim 14 , wherein at least one of the first and second interfaces comprises a NAND interface configured to transfer data using a NAND interface protocol.

21. The controller of claim 14 , wherein the data is modified by the controller.

22. The controller of claim 14 , wherein the data is modified by the host.

23. The controller of claim 14 , wherein the modification changes or adds information to a header of the data.

24. The controller of claim 23 , wherein the modification changes or adds information to one or more of the following in the header: a logical block address, a type field, a physical start address, a front end address block grouping, a run length of the data, and an endurance tag.

25. A controller comprising:
a first interface configured to transfer data between a host and the controller;
a second interface configured to transfer data between the controller and at least one flash memory device; and
circuitry operative to:
receive a source address and a copy-back read command from the host;
send the source address and the copy-back read command to the at least one flash memory device, wherein in response to receiving the source address and the copy-back read command, the at least one flash memory device reads data from the sourc

Assignees

• Sandisk Technologies Inc

Inventors

• Selinger Robert D
• Lin Gary
• Lassa Paul
• Wang Chaoyang

Classifications

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title