Method and apparatus for enabling a timing synchronization circuit

Patent metadata

Field	Value
Publication number	US-RE46005-E
Application number	US-80052007-A
Country	US
Kind code	E1
Filing date	May 4, 2007
Priority date	Jun 11, 2002
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal and a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal. The detection circuit is configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount. A method for synchronizing clock signals includes receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; controlling the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; and asserting the enable signal responsive to the phase alignment error exceeding a predetermined amount.

First claim

What is claimed:

1. A timing control circuit, comprising:
a synchronization circuit, comprising:
a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal;
a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal, control of the main delay line allowed responsive to assertion of an enable signal; and
a detection circuit configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount, said detection circuit comprising a noise filter for generating said enable signal.

2. The timing control circuit of claim 1 , wherein the detection circuit includes a first phase detector configured to compare the input clock signal and the feedback clock signal and assert the enable signal responsive to the feedback clock signal being out of phase with respect to the input clock signal.

3. The timing control circuit of claim 1 , wherein the detection circuit comprises:
a first phase detector having a first threshold and being configured to compare the input clock signal and the feedback clock signal and generate a shift signal responsive to the feedback clock signal being out of phase with respect to the input clock signal an amount greater than the first threshold; and
the noise filter coupled to the first phase detector and being configured to filter the shift signal to generate the enable signal.

4. The timing control circuit of claim 3 , wherein the noise filter is comprises an n-stage delay configured to assert the enable signal responsive to receiving n occurrences of the first shift signal.

5. The timing control circuit of claim 4 , wherein n is at least two.

6. The timing control circuit of claim 3 , wherein the detection circuit further comprises:
a second phase detector having a second threshold larger than the first threshold and being configured to compare the input clock signal and the feedback clock signal and assert the enable signal responsive to the feedback clock signal being out of phase with respect to the input clock signal an amount greater than the second threshold.

7. The timing control circuit of claim 1 , further comprising a first delay model configured to receive the output clock signal and generate the feedback clock signal.

8. The timing control circuit of claim 1 , wherein the synchronization circuit comprises a clock synchronized delay circuit.

9. The timing control circuit of claim 1 , wherein the synchronization circuit comprises a synchronous mirror delay circuit.

10. The timing control circuit of claim 1 , wherein the synchronization circuit further comprises:
a delay model configured to receive the input clock signal; and
a measurement delay line having a plurality of stages and being coupled to the delay model wherein the control circuit is configured to detect a stage of the measurement delay line where the input clock signal as delayed by the delay model and the measurement delay line is in phase with the input clock signal.

11. The timing control circuit of claim 10 , wherein the measurement delay line comprises a shift register and a plurality of control gates coupled to stages of the shift register.

12. The timing control circuit of claim 11 , wherein the main delay line comprises a plurality of serially cascaded delay elements, each transfer gate of the transfer gate array is associated with an associated one of the serially cascaded delay elements, and the an active transfer gate is configured to transfer the input clock signal as delayed by the delay model and the measurement delay line to its associated one of the serially cascaded delay elements.

13. The timing control circuit of claim 10 , wherein the control circuit comprises a latch array comprising a plurality of latches, each latch is coupled to a respective one of the stages of the measurement delay line, and one of the latches is active responsive to the input clock signal as delayed by the delay model and the measurement delay line being in phase with the input clock signal.

14. The timing control circuit of claim 13 , wherein the main delay line comprises a plurality of serially cascaded delay elements, each latch of the control circuit is coupled to an associated one of the serially cascaded delay elements, and the an active latch in the latch array enables its associated one of the serially cascaded delay elements.

15. The timing control circuit of claim 10 , wherein the control circuit comprises a transfer gate array comprising a plurality of transfer gates, each transfer gate is coupled to a respective one of the stages of the measurement delay line, and one of the transfer gates is active responsive to the input clock signal as delayed by the delay model and the measurement delay line being in phase with the input clock signal.

16. The timing control circuit of claim 1 , wherein the control circuit is configured to lock a current state of the main delay line responsive to the enable signal being deasserted.

17. A timing control circuit, comprising:
a synchronization circuit, comprising:
a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal;
a first delay model configured to receive the output clock signal and generate a feedback clock signal;
a control circuit configured to control the main delay line to vary the tune interval to synchronize the input clock signal with the feedback clock signal responsive to assertion of an enable signal; and
a detection circuit, comprising:
a first phase detector having a first threshold and being configured to compare the input clock signal and the feedback clock signal and generate a shift signal responsive to the feedback clock signal being out of phase with respect to the input clock signal an amount greater than the first threshold; and
a noise filter coupled to the first phase detector and being configured to filter the shift signal to generate the enable signal.

18. The timing control circuit of claim 17 , wherein the noise filter is comprises an n-stage delay configured to assert the enable signal responsive to receiving n occurrences of the first shift signal.

19. The timing control circuit of claim 18 , wherein n is at least two.

20. The circuit of claim 17 , wherein the detection circuit further comprises:
a second phase detector having a second threshold larger than the first threshold and being configured to compare the input clock signal and the feedback clock signal and assert the enable signal responsive to the feedback clock signal being out of phase with respect to the input clock signal an amount greater than the second thresh old.

21. The timing control circuit of claim 17 , wherein the synchronization circuit comprises a clock synchronized delay circuit.

22. The timing control circuit of claim 17 , wherein the synchronization circuit comprises a synchronous mirror delay circuit.

23. The timing control circuit of claim 17 , wherein the control circuit is configured to lock a current state of the main delay line responsive to the enable signal being deasserted.

Assignees

• Mikhalev Vladimir
• Lin Feng
• Micron Technology Inc

Inventors

• Mikhalev Vladimir
• Lin Feng

Classifications

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title