Non-volatile semiconductor storage device

Patent metadata

Field	Value
Publication number	US-RE45832-E
Application number	US-201314026844-A
Country	US
Kind code	E1
Filing date	Sep 13, 2013
Priority date	Nov 14, 2008
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

First claim

What is claimed is:

1. A non-volatile semiconductor storage device comprising:
a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and
a plurality of first selection transistors connected to one ends of the respective memory strings,
each of the memory strings comprising:
a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate;
a first electric charge storage layer formed to surround a side surface of the columnar portion; and
a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells,

each of the first selection transistors comprising:
a second semiconductor layer extending upward from a top surface of the columnar portion;
a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and
a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive layer functioning as a control electrode of a respective one of the first selection transistors,

the non-volatile semiconductor storage device further comprising a control circuit configured to cause, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

2. The non-volatile semiconductor storage device according to claim 1 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block.

3. The non-volatile semiconductor storage device according to claim 1 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.

4. The non-volatile semiconductor storage device according to claim 1 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.

5. The non-volatile semiconductor storage device according to claim 1 , wherein
after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

6. The non-volatile semiconductor storage device according to claim 5 , wherein
the control circuit is configured to generate a GIDL current near a gate of one of the first selection transistors connected to an unselected one of the memory strings to boost a voltage at the second semiconductor layer to a first voltage by the GIDL current,
thereby discharging electric charges stored in the second electric charge storage layer.

7. The non-volatile semiconductor storage device according to claim 1 , wherein
the control circuit causes electric charges to be accumulated in the second electric charge storage layer by boosting in a step-like manner to be applied to a gate of one of the first selection transistors connected to an unselected one of the memory strings.

8. The non-volatile semiconductor storage device according to claim 1 , comprising:
a plurality of second selection transistors connected to the other ends of the memory strings,
wherein each of the second selection transistors comprises:
a third semiconductor layer extending downward from a bottom surface of the first semiconductor layer;
a third electric charge storage layer formed to surround a side surface of the third semiconductor layer; and
a third conductive layer formed to surround a side surface of the third semiconductor layer as well as the third electric charge storage layer, the third conductive layer functioning as a control electrode of a respective one of the second selection transistors, and

prior to reading data from a selected one of the memory strings, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings.

9. The non-volatile semiconductor storage device according to claim 8 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block.

10. The non-volatile semiconductor storage device according to claim 8 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks.

11. The non-volatile semiconductor storage device according to claim 8 , wherein
a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and
prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks.

12. The non-volatile semiconductor storage device according to claim 8 , wherein
after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings.

13. The non-volatile semicond

Assignees

• Toshiba Kk

Inventors

• Maeda Takashi
• Iwata Yoshihisa

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title