Radio-frequency signal processing systems and methods
US-2024333403-A1 · Oct 3, 2024 · US
Systems and methods for randomizing component mismatch in an ADC
USRE45798E · US · E1
| Field | Value |
|---|---|
| Publication number | US-RE45798-E |
| Application number | US-201414473745-A |
| Country | US |
| Kind code | E1 |
| Filing date | Aug 29, 2014 |
| Priority date | Nov 7, 2011 |
| Publication date | Nov 10, 2015 |
| Grant date | Nov 10, 2015 |
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Abstract
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Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.
First claim
Opening claim text (preview).
What is claimed is: 1. An analog to digital converter (ADC) circuit comprising: an ADC input for receiving an analog input signal; a memory having preconfigured ordered sets of codes; a digital sequence generator configured to provide random numbers to the memory; at least one Flash reference generation digital to analog converter (FRGD), each FRGD having an input coupled to the digital sequence generator and an output configured to provide a reference voltage level; and a…
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- H04B17/102Primary
Electricity · mapped topic
- H03M1/0673Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent USRE45798E cover?
- Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an outp…
- Who is the assignee on this patent?
- Linear Techn Inc
- What technology area does this patent fall under?
- Primary CPC classification H04B17/102. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (E1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).