Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
USRE45697E · US · E1
| Field | Value |
|---|---|
| Publication number | US-RE45697-E |
| Application number | US-201414242610-A |
| Country | US |
| Kind code | E1 |
| Filing date | Apr 1, 2014 |
| Priority date | Dec 31, 2007 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.
Opening claim text (preview).
What is claimed is: 1. A method for storing information in a non-volatile memory, said method comprising: determining a starting key based upon a seed key and a logical page address associated with a group of data; randomizing the group of data using a deterministic sequence of keys corresponding to the starting key; storing the randomized group of data into a physical page of the non-volatile memory; and storing, into the physical page of the non-volatile memory, additional…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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